On Wed, Nov 16, 2005 at 12:47:31PM +0100, Florian Schirmer wrote: > Hi, > > >>The SYPCR register can be set only _once_ at machine startup and the > >>bootloader in question does not have an option to change the mode. Many > >>bootloaders probably dont. > > Okay, i was asuming you have control over the bootloader. > > >Updated patch addresses code duplication issue you mentioned and also > >adds an error message in case timer interrupt frequency is higher > >than the watchdog frequency. > > > >Can I add your Signed-off-by in case you're OK with it? > > Maybe i'm missing something obvious, but why is the interrupt driven > reaming code not working for your configuration. Are you using the PIT > for something else?
Nope. Anyway, the SWRI bit selects interrupt (0) or reset mode (1) for the watchdog. On reset mode no interrupt is sent to the kernel - the watchdog logic resets the system with HRESET. So, the timer in m8xx_wdt is _required_ for reset mode. Does that make sense? > Otherwise i'm fine with the patch. Feel free to add my Signed-off-by line. Ok, lets sort this out first. I wonder how interrupt mode is supposed to work, because the manual states that in interrupt mode (SWRI == 0) an NMI (IRQ0) is triggered, which jumps to 0x100 exception vector (SW reset). Maybe I'm misunderstanding the interrupt mode? Folks who wrote the patch claim it works on their 8xx's (as can be found on mailing list archives).
