On Thu, 2004-03-11 at 01:14, listmember at orkun.us wrote: > Kenneth, >
> However, I think, code could be enhanced to reset the SR bit, "only" for > level triggered interrupts and leave edge triggered interrupts alone. This > would require looking at UIC0_TR register as well. Yes If you could do a patch for this for level triggered only it would be good. I can't see this affecting anything negative so it should be no problem getting it integrated. ** Sent via the linuxppc-embedded mail list. See http://lists.linuxppc.org/
