Hi, Dan and Mark! Dan Malek wrote: > On Jul 1, 2005, at 10:15 AM, Mark Chambers wrote: > >> Is the SRAM being cached? I don't think the CPU will generate bursts >> unless it's cached, right? > > I don't really remember :-) I know the 8xx will not burst if the line > isn't > cached, and I know the 7xxx will. I thought the 82xx and 85xx would > also burst if you had sufficient sequential operations queued. On > 83/85xx you have to further qualify the discussion based upon the DDR2 > or the local bus interface :-) The CPM and DMA will burst on all > buses for 8xx/82xx/83xx/85xx if the memory controller is configured > to do so.
Thanks, for your comments! I'll have a look at it during the next days and let you know about my mileage :-) Greets, Clemens Koller _______________________________ R&D Imaging Devices Anagramm GmbH Rupert-Mayer-Str. 45/1 81379 Muenchen Germany http://www.anagramm.de Phone: +49-89-741518-50 Fax: +49-89-741518-19
