Here are additional register definitions for the MPC52xx. CDM clock
enables and port config bit settings in mpc52xx.h. Registers needed
to support non-UART PSC modes in mpc52xx_psc.h. Drivers which use
these regs/bits are to follow once I'm happy with them, but I thought
that others may be interested in them now.
Cheers,
g.
Signed-off-by: Grant Likely <grant.likely at gdcanada.com>
General Dynamics Canada, Ltd. relinquishes copywrite on this patch to
the public domain
--- k/include/asm-ppc/mpc52xx.h (mode:100644)
+++ l/include/asm-ppc/mpc52xx.h (mode:100644)
@@ -146,6 +146,28 @@ enum ppc_sys_devices {
#define MPC52xx_XLB_ARB_IRQ (MPC52xx_PERP_IRQ_BASE + 21)
#define MPC52xx_BDLC_IRQ (MPC52xx_PERP_IRQ_BASE + 22)
+/* CDM Cloke enable bits */
+#define MPC52xx_CDM_CLKENABLE_MEM_CLK (0x00080000)
+#define MPC52xx_CDM_CLKENABLE_PCI_CLK (0x00040000)
+#define MPC52xx_CDM_CLKENABLE_LPC_CLK (0x00020000)
+#define MPC52xx_CDM_CLKENABLE_SIT_CLK (0x00010000)
+#define MPC52xx_CDM_CLKENABLE_SCOM_CLK (0x00008000)
+#define MPC52xx_CDM_CLKENABLE_ATA_CLK (0x00004000)
+#define MPC52xx_CDM_CLKENABLE_ETH_CLK (0x00002000)
+#define MPC52xx_CDM_CLKENABLE_USB_CLK (0x00001000)
+#define MPC52xx_CDM_CLKENABLE_SPI_CLK (0x00000800)
+#define MPC52xx_CDM_CLKENABLE_BDLC_CLK (0x00000400)
+#define MPC52xx_CDM_CLKENABLE_IRRX_CLK (0x00000200)
+#define MPC52xx_CDM_CLKENABLE_IRTX_CLK (0x00000100)
+#define MPC52xx_CDM_CLKENABLE_PSC345_CLK (0x00000080)
+#define MPC52xx_CDM_CLKENABLE_PSC2_CLK (0x00000040)
+#define MPC52xx_CDM_CLKENABLE_PSC1_CLK (0x00000020)
+#define MPC52xx_CDM_CLKENABLE_PSC6_CLK (0x00000010)
+#define MPC52xx_CDM_CLKENABLE_MSCAN_CLK (0x00000008)
+#define MPC52xx_CDM_CLKENABLE_I2C_CLK (0x00000004)
+#define MPC52xx_CDM_CLKENABLE_TIMER_CLK (0x00000002)
+#define MPC52xx_CDM_CLKENABLE_GPIO_CLK (0x00000001)
+
/* ======================================================================== */
@@ -266,6 +288,49 @@ struct mpc52xx_rtc {
};
/* GPIO */
+#define PORT_CONFIG_CS1 0x80000000
+#define PORT_CONFIG_ALT_MASK 0x30000000
+#define PORT_CONFIG_CS7 0x08000000
+#define PORT_CONFIG_CS6 0x04000000
+#define PORT_CONFIG_ATA 0x03000000
+#define PORT_CONFIG_IR_USB_CLK 0x00800000
+#define PORT_CONFIG_IRDA_MASK 0x00700000 /* PSC6 */
+#define PORT_CONFIG_IRDA_GPIO 0x00000000
+#define PORT_CONFIG_IRDA_UART 0x00500000
+#define PORT_CONFIG_IRDA_CODEC 0x00700000
+#define PORT_CONFIG_ETHER_MASK 0x000F0000
+#define PORT_CONFIG_PCI_DIS 0x00008000
+#define PORT_CONFIG_USB_SE 0x00004000 /* Single ended mode */
+#define PORT_CONFIG_USB_MASK 0x00004000 /* (USB1 or 2 UARTs) */
+#define PORT_CONFIG_USB_USB 0x00001000
+#define PORT_CONFIG_USB_2UART 0x00002000
+#define PORT_CONFIG_PSC3_MASK 0x00000F00
+#define PORT_CONFIG_PSC3_GPIO 0x00000000
+#define PORT_CONFIG_PSC3_USB2 0x00000100
+#define PORT_CONFIG_PSC3_UART 0x00000400
+#define PORT_CONFIG_PSC3_UARTE_CD 0x00000500
+#define PORT_CONFIG_PSC3_CODEC 0x00000600
+#define PORT_CONFIG_PSC3_CODEC_MCLK 0x00000700
+#define PORT_CONFIG_PSC3_SPI 0x00000800
+#define PORT_CONFIG_PSC3_SPI_UART 0x00000C00
+#define PORT_CONFIG_PSC3_SPI_UARTE 0x00000D00
+#define PORT_CONFIG_PSC3_SPI_CODEC 0x00000E00
+#define PORT_CONFIG_PSC2_MASK 0x00000070
+#define PORT_CONFIG_PSC2_GPIO 0x00000000
+#define PORT_CONFIG_PSC2_CAN 0x00000010
+#define PORT_CONFIG_PSC2_AC97 0x00000020
+#define PORT_CONFIG_PSC2_UART 0x00000040
+#define PORT_CONFIG_PSC2_UARTE_CD 0x00000050
+#define PORT_CONFIG_PSC2_CODEC 0x00000060
+#define PORT_CONFIG_PSC2_CODEC_MCLK 0x00000070
+#define PORT_CONFIG_PSC1_MASK 0x00000007
+#define PORT_CONFIG_PSC1_GPIO 0x00000000
+#define PORT_CONFIG_PSC1_AC97 0x00000002
+#define PORT_CONFIG_PSC1_UART 0x00000004
+#define PORT_CONFIG_PSC1_UARTE_CD 0x00000005
+#define PORT_CONFIG_PSC1_CODEC 0x00000006
+#define PORT_CONFIG_PSC1_CODEC_MCLK 0x00000007
+
struct mpc52xx_gpio {
u32 port_config; /* GPIO + 0x00 */
u32 simple_gpioe; /* GPIO + 0x04 */
--- k/include/asm-ppc/mpc52xx_psc.h (mode:100644)
+++ l/include/asm-ppc/mpc52xx_psc.h (mode:100644)
@@ -72,6 +72,51 @@
#define MPC52xx_PSC_D_CTS 0x10
#define MPC52xx_PSC_D_DCD 0x20
+/* PSC Serial Interface Control Register (SICR) bits */
+/* SICR Field masks */
+#define MPC52xx_PSC_SICR_ACRB 0x80000000
+#define MPC52xx_PSC_SICR_AWR 0x40000000
+#define MPC52xx_PSC_SICR_DTS1 0x20000000
+#define MPC52xx_PSC_SICR_SHDIR 0x10000000
+#define MPC52xx_PSC_SICR_SIM 0x0F000000
+#define MPC52xx_PSC_SICR_GENCLK 0x00800000
+#define MPC52xx_PSC_SICR_MULTIWD 0x00400000
+#define MPC52xx_PSC_SICR_CLKPOL 0x00200000
+#define MPC52xx_PSC_SICR_SYNCPOL 0x00100000
+#define MPC52xx_PSC_SICR_CELLSLAVE 0x00080000
+#define MPC52xx_PSC_SICR_CELL2XCLK 0x00040000
+#define MPC52xx_PSC_SICR_SPI 0x00008000
+#define MPC52xx_PSC_SICR_MSTR 0x00004000
+#define MPC52xx_PSC_SICR_CPOL 0x00002000
+#define MPC52xx_PSC_SICR_CPHA 0x00001000
+#define MPC52xx_PSC_SICR_USEEOF 0x00000800
+/* Operation modes */
+#define MPC52xx_PSC_SICR_SIM_UART 0x00000000
+#define MPC52xx_PSC_SICR_SIM_UART_DCD 0x08000000
+#define MPC52xx_PSC_SICR_SIM_CODEC8 0x01000000
+#define MPC52xx_PSC_SICR_SIM_CODEC16 0x02000000
+#define MPC52xx_PSC_SICR_SIM_AC97 0x03000000
+#define MPC52xx_PSC_SICR_SIM_SIR 0x04000000
+#define MPC52xx_PSC_SICR_SIM_SIR_DCD 0x0C000000
+#define MPC52xx_PSC_SICR_SIM_MIR 0x05000000
+#define MPC52xx_PSC_SICR_SIM_FIR 0x06000000
+#define MPC52xx_PSC_SICR_SIM_CODEC24 0x07000000
+#define MPC52xx_PSC_SICR_SIM_CODEC32 0x0F000000
+
+/* IRCR1 bit masks */
+#define MPC52xx_PSC_IRCR1_FD 0x04
+#define MPC52xx_PSC_IRCR1_SIPEN 0x02
+#define MPC52xx_PSC_IRCR1_SPUL 0x01
+
+/* IRCR2 bit masks */
+#define MPC52xx_PSC_IRCR2_SIPREQ 0x04
+#define MPC52xx_PSC_IRCR2_ABORT 0x02
+#define MPC52xx_PSC_IRCR2_NXTEOF 0x01
+
+/* Codec Clock Register fields */
+#define MPC52xx_PSC_CCR_FRAME_SYNC_DIV 0xFF00
+#define MPC52xx_PSC_CCR_BIT_CLK_DIV 0xFF00
+
/* PSC mode fields */
#define MPC52xx_PSC_MODE_5_BITS 0x00
#define MPC52xx_PSC_MODE_6_BITS 0x01
