Hi
Had a look at my old driver and it needs a little care.
Basically this block has changed
> + if(count > 16){
> + /* Chip bug, set enable here */
> + local_irq_save(flags);
> + i2c->i2c_i2cmr = 0x13; /* Enable some interupts */
> + i2c->i2c_i2cer = 0xff;
> + i2c->i2c_i2mod |= 1; /* Enable */
> + i2c->i2c_i2com |= 0x80; /* Begin transmission */
> +
> + /* Wait for IIC transfer */
> + tmo = interruptible_sleep_on_timeout(&iic_wait,1*HZ);
> + local_irq_restore(flags);
> + } else { /* busy wait for small transfers, its faster */
> + i2c->i2c_i2cmr = 0x00; /* Disable I2C interupts */
> + i2c->i2c_i2cer = 0xff;
> + i2c->i2c_i2mod |= 1; /* Enable */
> + i2c->i2c_i2com |= 0x80; /* Begin transmission */
> + tmo = jiffies + 1*HZ;
> + /* Busy wait, with a timeout */
> + while(!(i2c->i2c_i2cer & 0x11 || time_after(jiffies, tmo)));
> + }
into
> + /* Chip bug, set enable here */
> + local_irq_save(flags);
> + i2c->i2c_i2cmr = 0x13; /* Enable some interupts */
> + i2c->i2c_i2cer = 0xff;
> + i2c->i2c_i2mod |= 1; /* Enable */
> + i2c->i2c_i2com |= 0x80 | 0x01; /* Begin transmission and force
> master.
Some errors(CL) clears the M/S
bit */
> +
> + /* Wait for IIC transfer */
> + tmo = interruptible_sleep_on_timeout(&iic_wait,1*HZ);
> + local_irq_restore(flags);
I have done this for cpm_iic_read, cpm_iic_write and cpm_iic_try_address.
Also note the the addition of "| 0x01" to i2c->i2c_i2com.
