> The book implicitly focuses on x86 driver developers, that's > why you don't get an explicit statement about this... > "everything" is PCI in that world. > > read*/write* and ioread*/iowrite* generate outbound little > endian cycles on ALL arches, period. They are intended > only for PCI use and have generic names only because of > the assumption that "all the world is a PC". > > Now, what it takes to to generate outbound little endian cycles > varies. On some arches, it's just a store (native LE) on > other arches, it's a reversed store (PPC), others still configure > their PCI bridge hardware to do byte swapping in hardware (typically > if their arch doesn't have a simple byte-swapping store like PPC). > > The example you cite on pg. 453 of Rubini looks broken for BE > systems. It works on LE systems since cpu_to_le32() does nothing > and writel is a simply dereference. That's pure luck. On PPC, > for example, that would write a big endian bus_addr to the fictitious > PCI device which is not what they want.
Great! An authoritive answer! Re: endianness, even cooler on the 440EP, in your mmap() implementation you can set the _PAGE_ENDIAN flag, and user-space will see the PCI device in little endian format. Fun stuff! Thanks Matt. Dave
