More efficient would be to lock the exception handlers in L1 cache. I don't know the access rate of DPRAM on 870? Should be bus speed? So, DPRAM and external memory would be same access time unless the electrical characteristics of RAM vs. DPRAM technology is different. -- Atul
- kernel startup Wolfgang Denk
- kernel startup Wolfgang Denk
- kernel startup [EMAIL PROTECTED]
- kernel startup [EMAIL PROTECTED]
- kernel startup Kumar Gala
- kernel startup Wolfgang Denk
- kernel startup [EMAIL PROTECTED]
- kernel startup [EMAIL PROTECTED]
- kernel startup Wolfgang Denk
- kernel startup [EMAIL PROTECTED]
- kernel startup [EMAIL PROTECTED]