Subject: PPC8272 - FCC2 transmitter underrun Description: On a board with PPC8272 we get "transmitter underrun" interrupt from the FCC2.
The BD and Buffers are on an external RAM on the 60x. It looks like getting the READY bit in the current BD with a perfectly good Buffer immidiatly brings up the interrupt. there are two underrun reasons : 1. If TxBD[L] (last buffer in the frame) is cleared when the end of the BD is reached and the transmitter moves immediately to the next buffer to begin transmission. Failure to provide the next buffer in time causes a transmit underrun. 2. If the CPM is heavy loaded and (because of bus latency) the SDMA cannot fill the FIFO from external memory, a transmit underrun occurs. But i've stepped with an ice and checked both -looked at the L bit and halted the cpu right after the setting of the Ready bit. -------------- next part -------------- An HTML attachment was scrubbed... URL: http://ozlabs.org/pipermail/linuxppc-embedded/attachments/20050606/18206aa1/attachment.htm
