Todd Poynor wrote:
>
> Noticed that the order of clearing the old transfer mode bits and
> setting the p_dma_ch->mode bits is reversed in the new patch, not sure
> if this causes problems:
>
> + tmp_cntl |= (p_dma_ch->mode | DMA_CH_ENABLE);
> +
> + switch (dmanr) {
> + case 0:
> + control = mfdcr(DCRN_DMACR0);
> + control |= tmp_cntl;
> + control &= ~(DMA_TM_MASK | DMA_TD); /* clear all
> mode bits */
>
> This seems to set and then clear the p_dma_ch->mode bits in control
> prior to writing to the DMACR, a problem?
>
>
> --
> Todd
>
>
>
>
>
Here is a patch that should address the above issue. I put in
additional checks for if a the current dma channel is all ready claimed
and if the requestion channel is greater than max dma channels.
dma_enable no longer clears mode bits. ( TODO: should document 4xx dma
usage)
Armin
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