On Wed, Apr 26, 2006 at 07:32:13PM -0400, Dan Malek wrote:
>
> On Apr 26, 2006, at 7:50 AM, David Jander wrote:
>
> > Yes, MPC852T is supported, although I might add that I have been
> > using 2.6.14
> > and 2.6.15 sucessfully with our own MPC852T-based board, but 2.6.16
> > did not
> > boot and as of today I don't know why, or whether this is an issue
> > at all
> > with boards other than ours.
>
> There is a horrible bug in the 8xx TLB miss handler that is in the
> 2.6.16
> sources. I don't know when it appeared. Enable the CPU6 Errata
> workaround to see if that solves the problem and please report back
> to me. I'm working on a solution.
Hi Dan,
Shame on me! I screwed up.
David, can you please try the following patch on top of vanilla v2.6.16?
The large TLB change introduced in v2.6.16 (which is broken as is for
configurations without CPU6 errata enabled as Dan noted) should boost
performance significantly, so you might want to rerun the lmbench
tests...
diff --git a/arch/ppc/kernel/head_8xx.S b/arch/ppc/kernel/head_8xx.S
index ec53c7d..7a2f205 100644
--- a/arch/ppc/kernel/head_8xx.S
+++ b/arch/ppc/kernel/head_8xx.S
@@ -355,9 +355,7 @@ #endif
. = 0x1200
DataStoreTLBMiss:
-#ifdef CONFIG_8xx_CPU6
stw r3, 8(r0)
-#endif
DO_8xx_CPU6(0x3f80, r3)
mtspr SPRN_M_TW, r10 /* Save a couple of working registers */
mfcr r10
@@ -417,9 +415,7 @@ #endif
lwz r11, 0(r0)
mtcr r11
lwz r11, 4(r0)
-#ifdef CONFIG_8xx_CPU6
lwz r3, 8(r0)
-#endif
rfi
/* This is an instruction TLB error on the MPC8xx. This could be due
