http://www.freescale.com/webapp/sps/utils/SingleFaq.jsp?FAQ-11241.xml
"Question. Board hangs when the 8260 data cache is enabled. Answer. We have found that in some systems, changing the pipline depth to 0 in the BCR register (BCR[PLDP] = 1) fixes any data cache issues." I don't know what those "some systems" are, but it seems that on all the others the pipeline depth must be set to 1 (BCR[PLDP] = 0). I don't know why, and it seems that Freescale doesn't either. Laurent Pinchart
