More information... > > Did you enable Memory Read Multiple command of your PCI master? > > Thanks for the clue. I'm trying to figure out how to do this. The PCI > master is a Tundra TSI148 VME-PCI bridge. The documentation says it > supports the PCI read multiple cycle, but so far I haven't found a > register to specifically configure it. I'll check the C/BE lines to see > if a PCI read multiple cycle is being issued. >
After grepping through the Tundra documentation more closely, I found this tidbit: "Memory read multiple: The memory read multiple command is used when the requested byte count is greater than 32 bytes." > I have confirmed that 64 bytes are being transferred before the MPC85xx > disconnects the transfer. If the PCI master initiates a 32 byte or 64 > byte read, the MPC85xx does not disconnect the transfer. > After scaning more logic analyzer captures, I noticed that occasionally the MPC85xx inserts additional wait states (by deasserting TRDY#) after only 32 bytes have been transferred. So it definitely appears that (the way I have things configured now) there's a 20-80ns delay after 1 cache line is read, and the MPC85xx disconnects transfers that are larger than 2 cache lines. Tim
