Hi, I am following the errata at the following location and need to implement CPU_162, CPU_197 & CPU_212 for PPC405F6X1 core on Xilinx Ml403 board ( ftp://ftp.xilinx.com/pub/documentation/misc/ppc405f6v5_2_0.pdf )
Can anyone suggest the instructions needed to be implemented for these errata. CPU_162 : When in Real Mode , the 405 core may errantly make speculative instruction fetches from guarded storage. CPU_197 : Incorrect Real mode attributes may be used when accessing the last instruction in a 128 MB region. CPU_212 thanks yogi -------------- next part -------------- An HTML attachment was scrubbed... URL: http://ozlabs.org/pipermail/linuxppc-embedded/attachments/20060725/7a0e58f1/attachment.htm
