Justin (Gus) Hurwitz wrote:
> #else
> __asm__ __volatile__("\n\
> 1: lwzx %0,0,%3\n\
> add %0,%2,%0\n\
> stwx %0,0,%3"
> : "=&r" (t), "=m" (v->counter)
> : "r" (a), "r" (v), "m" (v->counter)
> : "cc");
> #endif /* CONFIG_NO_ATOMICS */
Last time this came up I pointed out that lwarx/stwcx are for locking
against interrupts as well as against other CPUs. You don't seem to have
anything in your atomic routine to prevent interrupts occurring between
the load and the store.
--
Adrian Cox http://www.humboldt.co.uk/
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