Greetings Just been debugging some exception handling stuff and I'm sure that the combination of bdi2000, gdb & ddd I have is suffering an 'off by one' error in the register display
e.g. I see this srr0 0x818000 srr1 0x3fca360 tbl 0x9002 But the sensible values of srr0 & srr1 should be srr0 0x3fca360 srr1 0x9002 so that fault address is in srr0 and the bits from MSR (EE, ME and RI) are set in srr1. Anyone seen this and where is the slippage coming from (r0 to r31 look OK as far as I can see but don't really know about the others!!). I've tried both REGLIST ALL and REGLIST SPR in the bdi2000 config but it doesn't appear to make a difference. bdi2000 code=1.13, fpga=1.02 mpc8xx target gdb 5.3 ddd 3.3.1 Many thanks -- Robin Gilks Senior Design Engineer Phone: (+64)(3) 357 1569 Tait Electronics Fax : (+64)(3) 359 4632 PO Box 1645 Christchurch Email : robin.gilks at tait.co.nz New Zealand ======================================================================= This email, including any attachments, is only for the intended addressee. It is subject to copyright, is confidential and may be the subject of legal or other privilege, none of which is waived or lost by reason of this transmission. If the receiver is not the intended addressee, please accept our apologies, notify us by return, delete all copies and perform no other act on the email. Unfortunately, we cannot warrant that the email has not been altered or corrupted during transmission. =======================================================================
