On Dienstag 26 Oktober 2004 22:58, Matt Porter wrote: > Always disable L2 cache on PPC440GX. All revs/speeds of silicon > have parity error problems despite errata claims to the contrary. > Signed-off-by: Matt Porter <mporter at kernel.crashing.org>
Hi Matt, is there any test, with which you can reproduce these failures? We have here custom boards based on the 440GX latest rev and we need to use them with enabled L2 cache... TIA, Gerhard
