Hi Matthias, > I must admit, that the AMCC PowerPC's PCI interrupt capabilities could > be better:-) In both directions the host CPU has to do PCI > configuration cycles either to generate or acknowledge an interrupt. > The later is problematic for some OS coming from Redmond: you > have to do pci configuration cycles from interrupt level - and > these OS do not 'like' that.
Yikes. I'm sure there were some headaches there. > In later designs and where possible we also switched to alternative > interrupt mechanisms (GPIO for target to host and gated flags in FPGA > registers for the other direction). Multiple interrupt sources > are identified by messages that are written to the other sides > memory. > > I think we should stop this discussion because its a little bit > off-topic on this list. I think this particular piece of info is important on this list. It'll help those looking for processor options that happen to search back through the list messages. I'm done now, I just wanted to satisfy my curiosity (and I did learn how the host can interrupt the core!). I know that Leonid has hardware with these CPUs on them, and he wanted some feedback on the AMCCs as target processor. I'd eliminated the processor before getting it fully into a design; so your experience is a little further on. However, the conclusion remains the same; try to avoid using the 440EP as a PCI target device. Cheers, Dave _______________________________________________ Linuxppc-embedded mailing list Linuxppc-embedded@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-embedded
