Greetings! Thank you for your interest.

The basic idea is to adjust PWM output depending on the captured CPTS
timestamps, thus eliminating any software latencies.

1. Start DM timer free-running as a 1 sec period PWM.
2. Enable generation of CPTS hardware timestamp events on this timer.
3. On each CPTS HW_TS event, calculate the offset and change TLDR value.

One person (I am not sure I can tell his name) did some improvements to
this:

1. He starts PWM close to nearest second (from HW_TS_PUSH event), and uses
a simple PI controller for TLDR.
2. He also enables the actual PWM hardware output after a first few
adjustment pulses.

Best regards,
Kim Yursen

2016-11-30 23:59 GMT+03:00 David Cemin <david.ce...@coveloz.com>:

> Hi Kim,
>
>
> On this thread 
> (https://www.mail-archive.com/linuxptp-devel@lists.sourceforge.net/msg01033.html)
>  you wrote this
>
>
> >We implemented PPS output signal through AM335x Dual-Mode Timer >running in
> >the PWM mode with SCLK frequency.
>
> >This is more accurate than software GPIO output because the CPTS >on the
> >AM335x
> >can generate hardware timestamp event on the rising edge of the >DMTimer,
> >making it possible to synchronize PPS with the CPTS internal clock <counter.
>
> Can you (or someone else on this list) give more details on how did you 
> achieve this? Im not sure sure you actually got the pps output sync to PTP on 
> this approach. How did you connect the CPTS to the PWM ?
>
>
> Thanks
>
>
> --
>
> David
>
>
>
>
>
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