From: Vincent Cheng <vincent.cheng...@renesas.com>
When clock stepping is unable to happen instantaneously the subsequent
timestamps after a clock step does not reflect the step result and
undesired clock freq and clock step adjustments will occur.
When using ts2phc to synchronize timestamping clock using external
1 PPS, it could take up to 1 second for the timestamps to reflect the
clock step.
step_window, when set, indicates the time in seconds after a clock
step in which the clock servo will not do any frequency or step
adjustments.
Below example illustrates the problem for 16 PPS when clock step
does not occur before the next set of timestamps are received.
Debug statements were added to show T1 and T2 timestamps and the freq
and step requests at clock_sychronize() for SERVO_JUMP.
ptp4l[255352.651]: selected best master clock 00b0ae.fffe.02e810
ptp4l[255352.651]: port 1: LISTENING to UNCALIBRATED on RS_SLAVE
ptp4l[255352.717]: debug: T1: 1611934788908411436 T2: 10341336582
...
ptp4l[255352.904]: master offset -1611934778567080326 s0 freq -128 path
delay 5436
ptp4l[255352.967]: debug: T1: 1611934789158411436 T2: 10591336566
ptp4l[255352.967]: debug: adj freq -159.999967232
ptp4l[255352.971]: debug: step 1611934778567080308
...
ptp4l[255353.217]: debug: T1: 1611934789408411436 T2: 10841336502
ptp4l[255353.217]: debug: adj freq 0.000027648
ptp4l[255353.221]: debug: step 1611934778567080368
At 16 PPS, the packet interval is 0.0625 seconds.
The first step occurs at [255352.971], T2 is around 10 seconds.
The next step occurs at [255353.221], T2 is still around 10 seconds.
In an ideal setup, the clock step would be reflected instantaneously
and the correct T2 should be around 1611934799 seconds.
Below shows result of adding step_window.
Clock step occurs at s1, SERVO_JUMP. s2 is SERVO_LOCKED.
The setup is using ts2phc to synhronize the network PHC to external timestamp
signal. The progation delay of the 1 PPS signals have a worst case of
2 seconds.
step_window is set to 0 (default 0), so retains original behavior,
ie. will use subsequent timestamps to calculate next clock adjustments.
logSyncInterval -4
logMinDelayReqInterval -4
first_step_threshold 0.001000000
step_threshold 0.000001000
step_window 0
ptp4l[527891.082]: port 1: LISTENING to UNCALIBRATED on RS_SLAVE
ptp4l[527891.211]: master offset -1612207328934216028 s0 freq +0 path
delay 5434
ptp4l[527891.278]: master offset -1612207328934216032 s1 freq -64 path
delay 5434
ptp4l[527891.336]: master offset -1612207328934216040 s0 freq -64 path
delay 5434
...
ptp4l[527891.399]: master offset -1612207328934216028 s0 freq -64 path
delay 5434
ptp4l[527892.028]: master offset -1612207328934216022 s1 freq -224 path
delay 5432
ptp4l[527892.086]: master offset -1612207328934215996 s0 freq -224 path
delay 5432
ptp4l[527892.148]: master offset -1612207328934215992 s0 freq -224 path
delay 5438
ptp4l[527892.215]: master offset 2418310993565784016 s1 freq +244000 path
delay 5438
ptp4l[527892.273]: master offset 6448829316065775199 s0 freq +244000 path
delay 5438
...
ptp4l[527892.965]: master offset 6448829316065728196 s1 freq +12880 path
delay 4838
ptp4l[527893.086]: master offset 6448829316065726790 s0 freq +12880 path
delay 5644
ptp4l[527893.148]: master offset 6448829316065725922 s0 freq +12880 path
delay 5708
ptp4l[527893.215]: master offset 7346469049727168082 s1 freq +244000 path
delay -448819866830715715
ptp4l[527893.273]: master offset 7346469049727153274 s0 freq +244000 path
delay -448819866830715715
ptp4l[527893.336]: master offset 7346469049727141992 s0 freq +244000 path
delay 8750
ptp4l[527893.403]: master offset 7346469049727127700 s1 freq +15328 path
delay 7786
ptp4l[527894.398]: rms 7346469049727119360 max 7346469049727121408 freq
+3737 +/- 6692 delay -13600602025167668 +/- 76936623361756672
ptp4l[527895.461]: rms 7346469049727117312 max 7346469049727117312 freq
-54 +/- 89 delay 5439 +/- 10
ptp4l[527896.586]: rms 7346469049727117312 max 7346469049727117312 freq
-47 +/- 48 delay 5436 +/- 7
...
The multiple clock steps (s1 - [527891.278], [527892.028], etc.) overlap
each other and causes convergence problems.
Setting step_window to 2:
logSyncInterval -4
logMinDelayReqInterval -4
first_step_threshold 0.001000000
step_threshold 0.000001000
step_window 2
ptp4l[527997.072]: port 1: LISTENING to UNCALIBRATED on RS_SLAVE
ptp4l[527997.201]: master offset -1612207446193442550 s0 freq +0 path
delay 5440
ptp4l[527997.268]: master offset -1612207446193442560 s1 freq -160 path
delay 5450
ptp4l[527997.451]: master offset -806103723193442530 s0 freq +1000000000
path delay 5424
ptp4l[527997.576]: master offset -193442508 s0 freq +192 path delay
5422
ptp4l[527997.701]: master offset -193442490 s0 freq +384 path delay
5436
ptp4l[527997.826]: master offset -193442512 s0 freq -320 path delay
5438
ptp4l[527997.951]: master offset -193442474 s0 freq +384 path delay
5444
ptp4l[527998.076]: master offset -193442464 s0 freq -64 path delay
5434
ptp4l[527998.201]: master offset -193442444 s0 freq +128 path delay
5422
ptp4l[527998.326]: master offset -193442454 s0 freq +0 path delay
5440
ptp4l[527998.451]: master offset -193442434 s0 freq +192 path delay
5432
ptp4l[527998.576]: master offset -193442412 s0 freq +192 path delay
5426
ptp4l[527998.701]: master offset -193442418 s0 freq -128 path delay
5440
ptp4l[527998.826]: master offset -193442410 s0 freq +128 path delay
5448
ptp4l[527998.951]: master offset -193442388 s0 freq +128 path delay
5442
ptp4l[527999.076]: master offset -193442380 s0 freq +128 path delay
5438
ptp4l[527999.201]: master offset -193442366 s0 freq +64 path delay
5436
ptp4l[527999.326]: master offset 59126 s0 freq -160 path delay
5444
ptp4l[527999.388]: master offset 59136 s0 freq -160 path delay
5442
ptp4l[527999.452]: master offset 59136 s1 freq -160 path delay
5442
ptp4l[527999.513]: master offset 49298 s0 freq +382394648 path delay
5442
ptp4l[528001.514]: port 1: UNCALIBRATED to SLAVE on MASTER_CLOCK_SELECTED
ptp4l[528002.451]: rms 173 max 292 freq +244 +/- 79 delay 5726 +/-
1210
ptp4l[528003.451]: rms 40 max 64 freq +6 +/- 54 delay 5439 +/- 9
ptp4l[528004.451]: rms 41 max 58 freq -76 +/- 18 delay 5438 +/- 9
ptp4l[528005.451]: rms 15 max 30 freq -73 +/- 12 delay 5438 +/- 7
ptp4l[528006.450]: rms 7 max 16 freq -31 +/- 28 delay 5440 +/- 7
The 1st clock step at [527997.268] is given a chance to complete. After
2 seconds, the master offset at [527999.326] properly reflects the results of
the 1st clock step.
Vincent Cheng (1):
clock: Introduce step_window to free run x seconds after a clock step.
clock.c | 40 ++++++++++++++++++++++++++++++++++++++++
config.c | 1 +
ptp4l.8 | 8 ++++++++
3 files changed, 49 insertions(+)
--
2.7.4
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