My system:
kernel 3.10.17
stmmac driver
In the file stmmac_hwstamp.c, in the function
stmmac_config_sub_second_increment(), the clock rate is
converted to nano seconds (using a formula that assumes the ptp_clock is 50Mhz)
and then
scaled depending on binary or digital rollover mode, and finally
written to the sub second increment register.
When I ponder the following line of code in this function (where "value" is
previously-read Time Stamp Control Register):
/* 0.465ns accuracy */
if (value & PTP_TCR_TSCTRLSSR)
data = (data * 100) / 465;
it says to me "if the PTP_TCR_TSCTRLSSR bit is SET (indicating digital rollover
mode) then scale
the sub-second increment value by .465 ns"
I'm confused however, because it seems to me that if the TSCTRLSSR bit is CLEAR
(indicating BINARY rollover mode)
that's when we require the .465ns scale factor (yes? no?)
Regards,
Tony "puzzled" Klein
MAX4G MPLS, MN
>
> As it is most likely the case and if you have any idea of the cause, do you
> think it is coming:
> - from the time management (adjust/set freq/time)
> - from the timestamping receive end on the hardware
>
> I think it is time to dig into the driver again (>,<).
>
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