Hi Richard,
thank you for your prompt reply.
> On Thu, Apr 06, 2017 at 04:58:18PM +0200, Richard Cochran wrote:
> >
> > On Thu, Apr 06, 2017 at 01:45:19PM +0200, Axel Holzinger wrote:
> > To me it looks like there is trouble correctly adjusting the frequency
of
> > the PHC, it's always remaining +1000000, but also delays are ridicously
high
> > and negative (that doesn't make sense, does it?).
>
> Does that SoC use the CPTS?
I do think so.
> Probably the input clock is wrong. Check the data sheet and the device
tree
> values for:
>
> cpts_clock_mult = <0x80000000>;
> cpts_clock_shift = <29>;
Well I'm no dts expert at all. I found in
ti-linux-kernel/arch/arm/boot/dts/am57xx-titanium.dts:
#include "dra74x.dtsi"
In dra74x.dtsi:
#include "dra7.dtsi"
In dra7.dtsi:
/ {
#address-cells = <1>;
#size-cells = <1>;
compatible = "ti,dra7xx";
interrupt-parent = <&crossbar_mpu>;
/*
* XXX: Use a flat representation of the SOC interconnect.
* The real OMAP interconnect network is quite complex.
* Since it will not bring real advantage to represent that in DT for
* the moment, just use a fake OCP bus entry to represent the whole
bus
* hierarchy.
*/
ocp {
compatible = "ti,dra7-l3-noc", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges;
ti,hwmods = "l3_main_1", "l3_main_2";
reg = <0x44000000 0x1000000>,
<0x45000000 0x1000>;
interrupts-extended = <&crossbar_mpu GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
<&wakeupgen GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
...
mac: ethernet@48484000 {
compatible = "ti,dra7-cpsw","ti,cpsw";
ti,hwmods = "gmac";
clocks = <&dpll_gmac_ck>, <&gmac_gmii_ref_clk_div>;
clock-names = "fck", "cpts";
cpdma_channels = <8>;
ale_entries = <1024>;
bd_ram_size = <0x2000>;
no_bd_ram = <0>;
rx_descs = <64>;
mac_control = <0x20>;
slaves = <2>;
active_slave = <0>;
cpts_clock_mult = <0x80000000>;
cpts_clock_shift = <29>;
reg = <0x48484000 0x1000
0x48485200 0x2E00>;
#address-cells = <1>;
#size-cells = <1>;
/*
* Do not allow gating of cpsw clock as workaround
* for errata i877. Keeping internal clock disabled
* causes the device switching characteristics
* to degrade over time and eventually fail to meet
* the data manual delay time/skew specs.
*/
ti,no-idle;
/*
* rx_thresh_pend
* rx_pend
* tx_pend
* misc_pend
*/
interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>;
ranges;
status = "disabled";
davinci_mdio: mdio@48485000 {
compatible = "ti,davinci_mdio";
#address-cells = <1>;
#size-cells = <0>;
ti,hwmods = "davinci_mdio";
bus_freq = <1000000>;
reg = <0x48485000 0x100>;
clocks = <&gmac_gmii_ref_clk_div>;
clock-names = "fck";
};
cpsw_emac0: slave@48480200 {
/* Filled in by U-Boot */
mac-address = [ 00 00 00 00 00 00 ];
};
cpsw_emac1: slave@48480300 {
/* Filled in by U-Boot */
mac-address = [ 00 00 00 00 00 00 ];
};
phy_sel: cpsw-phy-sel@4a002554 {
compatible = "ti,dra7xx-cpsw-phy-sel";
reg= <0x4a002554 0x4>;
reg-names = "gmii-sel";
};
};
...
};
...
};
So the values for cpts_clock_mult and cpts_clock_shift are configured like
you proposed.
Is there anything else I can check?
Thanks
Axel
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