Hi,
I'm working on a project where a Xilinx Zynq uses a DP83640 (eval board)
as the Ethernet PHY. I'm running Ubuntu/Linaro 15 on the Zynq's ARM
processor and successfully modified kernel options and
compiled/installed LinuxPTP to synchronize time over the network. Now I
would like to use the DP83640's configurable reference clock (output on
a GPIO pin) to clock logic in the FPGA section of the Zynq. To do that I
would need to read/write the DP83640's internal registers, but I don't
know how.
It seems that there is some functionality in setting the registers in
dp83640.c. In an earlier post in this list:
> (2) DP83640 Driver: I found several comments that the GPIOs of the
> PHYs should be connected together on order to be able to synchronize
> the two PHYs (recalibrate) but I did't find the detail information
> which GPIO of PHY 1should be connected to which GPIO of PHY 2.
If does not matter which GPIO. You can choose any one of these.
1, 2, 3, 4, 8, 9, 10, 11
The dp83640 driver has a module parameter that lets you configure
this.
In the code I see statements like this (e.g. line 678)
ext_write <http://lxr.free-electrons.com/ident?i=ext_write>(0, master,PAGE4
<http://lxr.free-electrons.com/ident?i=PAGE4>,PTP_CTL
<http://lxr.free-electrons.com/ident?i=PTP_CTL>,val
<http://lxr.free-electrons.com/ident?i=val>);
which seems to write to the PTP control register in page 4 of the
DP83640's memory. However I can't figure out how this would be used,
either through LinuxPTP or a separate user program. Any help would be
greatly appreciated.
Some more system info:
I'm using the xemacps driver for the Zynq MAC
root@pixie-net:~# dmesg | grep b000
[ 0.867840] mdio_bus ef2df0a4: /amba/ethernet@e000b000/mdio has
invalid PHY address
[ 1.010225] xemacps e000b000.ethernet: pdev->id -1, baseaddr
0xe000b000, irq 147
[ 3.486259] xemacps e000b000.ethernet eth1: renamed from eth0
[ 6.282066] xemacps e000b000.ethernet: GEM: phydev ef202c00,
phydev->phy_id 0x20005ce1, phydev->addr 0x0
[ 6.282097] xemacps e000b000.ethernet: phy_addr 0x0, phy_id 0x20005ce1
[ 6.282107] xemacps e000b000.ethernet: attach [NatSemi DP83640] phy
driver
[ 8.391352] xemacps e000b000.ethernet: Set clk to 0 Hz
[ 8.391367] xemacps e000b000.ethernet: link up (100/FULL)
Though there are some warnings, I get a working connection through our
local network
ethtool reports
root@pixie-net:~# ethtool -T eth1
Time stamping parameters for eth1:
Capabilities:
hardware-transmit (SOF_TIMESTAMPING_TX_HARDWARE)
hardware-receive (SOF_TIMESTAMPING_RX_HARDWARE)
hardware-raw-clock (SOF_TIMESTAMPING_RAW_HARDWARE)
PTP Hardware Clock: 0
Hardware Transmit Timestamp Modes:
off (HWTSTAMP_TX_OFF)
on (HWTSTAMP_TX_ON)
one-step-sync (HWTSTAMP_TX_ONESTEP_SYNC)
Hardware Receive Filter Modes:
none (HWTSTAMP_FILTER_NONE)
ptpv1-l4-event (HWTSTAMP_FILTER_PTP_V1_L4_EVENT)
ptpv2-l4-event (HWTSTAMP_FILTER_PTP_V2_L4_EVENT)
ptpv2-l2-event (HWTSTAMP_FILTER_PTP_V2_L2_EVENT)
ptpv2-event (HWTSTAMP_FILTER_PTP_V2_EVENT)
Running ptp4l on 2 systems connected though the local network, I see
them link up and adjust to an offset of a few hundred ns.
I should add that I did not (yet) find where/how to modify the xemacps
driver per https://lwn.net/Articles/392150/
1. Before mdio_register, add
bus->locktype = MDIOBUS_ATOMIC_RW;
2. In the .ndo_start_xmit function, add
skb_tx_timestamp()
3. In the NAPI poll function, add
skb_rx_timestamp()
and so the HW timestamping might have been provided by the Zynq's build
in TSU instead of the DP83640. How would you tell? Does it matter where
in the function one adds skb_tx_timestamp()?
Thanks for your help,
Wolfgang
--
Wolfgang Hennig
XIA LLC
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