On Tue Feb 4 22:50:16 2025 -0500, Richard Acayan wrote:
> The camera subsystem for the SDM670 the same as on SDM845 except with
> 3 CSIPHY ports instead of 4. Add support for the SDM670 camera
> subsystem.
> 
> Signed-off-by: Richard Acayan <mailingrad...@gmail.com>
> Reviewed-by: Bryan O'Donoghue <bryan.odonog...@linaro.org>
> Signed-off-by: Bryan O'Donoghue <bryan.odonog...@linaro.org>
> Signed-off-by: Hans Verkuil <hverk...@xs4all.nl>

Patch committed.

Thanks,
Hans Verkuil

 drivers/media/platform/qcom/camss/camss.c | 191 ++++++++++++++++++++++++++++++
 1 file changed, 191 insertions(+)

---

diff --git a/drivers/media/platform/qcom/camss/camss.c 
b/drivers/media/platform/qcom/camss/camss.c
index cfef1e4f211c..497235f47188 100644
--- a/drivers/media/platform/qcom/camss/camss.c
+++ b/drivers/media/platform/qcom/camss/camss.c
@@ -738,6 +738,185 @@ static const struct camss_subdev_resources vfe_res_660[] 
= {
        }
 };
 
+static const struct camss_subdev_resources csiphy_res_670[] = {
+       /* CSIPHY0 */
+       {
+               .regulators = { "vdda-phy", "vdda-pll" },
+               .clock = { "soc_ahb", "cpas_ahb",
+                          "csiphy0", "csiphy0_timer" },
+               .clock_rate = { { 0 },
+                               { 0 },
+                               { 0 },
+                               { 19200000, 240000000, 269333333 } },
+               .reg = { "csiphy0" },
+               .interrupt = { "csiphy0" },
+               .csiphy = {
+                       .hw_ops = &csiphy_ops_3ph_1_0,
+                       .formats = &csiphy_formats_sdm845
+               }
+       },
+
+       /* CSIPHY1 */
+       {
+               .regulators = { "vdda-phy", "vdda-pll" },
+               .clock = { "soc_ahb", "cpas_ahb",
+                          "csiphy1", "csiphy1_timer" },
+               .clock_rate = { { 0 },
+                               { 0 },
+                               { 0 },
+                               { 19200000, 240000000, 269333333 } },
+               .reg = { "csiphy1" },
+               .interrupt = { "csiphy1" },
+               .csiphy = {
+                       .hw_ops = &csiphy_ops_3ph_1_0,
+                       .formats = &csiphy_formats_sdm845
+               }
+       },
+
+       /* CSIPHY2 */
+       {
+               .regulators = { "vdda-phy", "vdda-pll" },
+               .clock = { "soc_ahb", "cpas_ahb",
+                          "csiphy2", "csiphy2_timer" },
+               .clock_rate = { { 0 },
+                               { 0 },
+                               { 0 },
+                               { 19200000, 240000000, 269333333 } },
+               .reg = { "csiphy2" },
+               .interrupt = { "csiphy2" },
+               .csiphy = {
+                       .hw_ops = &csiphy_ops_3ph_1_0,
+                       .formats = &csiphy_formats_sdm845
+               }
+       }
+};
+
+static const struct camss_subdev_resources csid_res_670[] = {
+       /* CSID0 */
+       {
+               .regulators = {},
+               .clock = { "cpas_ahb", "soc_ahb", "vfe0",
+                          "vfe0_cphy_rx", "csi0" },
+               .clock_rate = { { 0 },
+                               { 0 },
+                               { 100000000, 320000000, 404000000, 480000000, 
600000000 },
+                               { 384000000 },
+                               { 19200000, 75000000, 384000000, 538666667 } },
+               .reg = { "csid0" },
+               .interrupt = { "csid0" },
+               .csid = {
+                       .hw_ops = &csid_ops_gen2,
+                       .parent_dev_ops = &vfe_parent_dev_ops,
+                       .formats = &csid_formats_gen2
+               }
+       },
+
+       /* CSID1 */
+       {
+               .regulators = {},
+               .clock = { "cpas_ahb", "soc_ahb", "vfe1",
+                          "vfe1_cphy_rx", "csi1" },
+               .clock_rate = { { 0 },
+                               { 0 },
+                               { 100000000, 320000000, 404000000, 480000000, 
600000000 },
+                               { 384000000 },
+                               { 19200000, 75000000, 384000000, 538666667 } },
+               .reg = { "csid1" },
+               .interrupt = { "csid1" },
+               .csid = {
+                       .hw_ops = &csid_ops_gen2,
+                       .parent_dev_ops = &vfe_parent_dev_ops,
+                       .formats = &csid_formats_gen2
+               }
+       },
+
+       /* CSID2 */
+       {
+               .regulators = {},
+               .clock = { "cpas_ahb", "soc_ahb", "vfe_lite",
+                          "vfe_lite_cphy_rx", "csi2" },
+               .clock_rate = { { 0 },
+                               { 0 },
+                               { 100000000, 320000000, 404000000, 480000000, 
600000000 },
+                               { 384000000 },
+                               { 19200000, 75000000, 384000000, 538666667 } },
+               .reg = { "csid2" },
+               .interrupt = { "csid2" },
+               .csid = {
+                       .is_lite = true,
+                       .hw_ops = &csid_ops_gen2,
+                       .parent_dev_ops = &vfe_parent_dev_ops,
+                       .formats = &csid_formats_gen2
+               }
+       }
+};
+
+static const struct camss_subdev_resources vfe_res_670[] = {
+       /* VFE0 */
+       {
+               .regulators = {},
+               .clock = { "camnoc_axi", "cpas_ahb", "soc_ahb",
+                          "vfe0", "vfe0_axi" },
+               .clock_rate = { { 0 },
+                               { 0 },
+                               { 0 },
+                               { 100000000, 320000000, 404000000, 480000000, 
600000000 },
+                               { 0 } },
+               .reg = { "vfe0" },
+               .interrupt = { "vfe0" },
+               .vfe = {
+                       .line_num = 4,
+                       .has_pd = true,
+                       .pd_name = "ife0",
+                       .hw_ops = &vfe_ops_170,
+                       .formats_rdi = &vfe_formats_rdi_845,
+                       .formats_pix = &vfe_formats_pix_845
+               }
+       },
+
+       /* VFE1 */
+       {
+               .regulators = {},
+               .clock = { "camnoc_axi", "cpas_ahb", "soc_ahb",
+                          "vfe1", "vfe1_axi" },
+               .clock_rate = { { 0 },
+                               { 0 },
+                               { 0 },
+                               { 100000000, 320000000, 404000000, 480000000, 
600000000 },
+                               { 0 } },
+               .reg = { "vfe1" },
+               .interrupt = { "vfe1" },
+               .vfe = {
+                       .line_num = 4,
+                       .has_pd = true,
+                       .pd_name = "ife1",
+                       .hw_ops = &vfe_ops_170,
+                       .formats_rdi = &vfe_formats_rdi_845,
+                       .formats_pix = &vfe_formats_pix_845
+               }
+       },
+
+       /* VFE-lite */
+       {
+               .regulators = {},
+               .clock = { "camnoc_axi", "cpas_ahb", "soc_ahb",
+                          "vfe_lite" },
+               .clock_rate = { { 0 },
+                               { 0 },
+                               { 0 },
+                               { 100000000, 320000000, 404000000, 480000000, 
600000000 } },
+               .reg = { "vfe_lite" },
+               .interrupt = { "vfe_lite" },
+               .vfe = {
+                       .is_lite = true,
+                       .line_num = 4,
+                       .hw_ops = &vfe_ops_170,
+                       .formats_rdi = &vfe_formats_rdi_845,
+                       .formats_pix = &vfe_formats_pix_845
+               }
+       }
+};
+
 static const struct camss_subdev_resources csiphy_res_845[] = {
        /* CSIPHY0 */
        {
@@ -3246,6 +3425,17 @@ static const struct camss_resources sdm660_resources = {
        .link_entities = camss_link_entities
 };
 
+static const struct camss_resources sdm670_resources = {
+       .version = CAMSS_845,
+       .csiphy_res = csiphy_res_670,
+       .csid_res = csid_res_670,
+       .vfe_res = vfe_res_670,
+       .csiphy_num = ARRAY_SIZE(csiphy_res_670),
+       .csid_num = ARRAY_SIZE(csid_res_670),
+       .vfe_num = ARRAY_SIZE(vfe_res_670),
+       .link_entities = camss_link_entities
+};
+
 static const struct camss_resources sdm845_resources = {
        .version = CAMSS_845,
        .csiphy_res = csiphy_res_845,
@@ -3322,6 +3512,7 @@ static const struct of_device_id camss_dt_match[] = {
        { .compatible = "qcom,sc7280-camss", .data = &sc7280_resources },
        { .compatible = "qcom,sc8280xp-camss", .data = &sc8280xp_resources },
        { .compatible = "qcom,sdm660-camss", .data = &sdm660_resources },
+       { .compatible = "qcom,sdm670-camss", .data = &sdm670_resources },
        { .compatible = "qcom,sdm845-camss", .data = &sdm845_resources },
        { .compatible = "qcom,sm8250-camss", .data = &sm8250_resources },
        { .compatible = "qcom,sm8550-camss", .data = &sm8550_resources },

Reply via email to