On Wed Sep 30 14:41:30 2026 +0800, Hermes Wu wrote:
> it6625_get_pclk() manually assembled a big-endian u32 from a 4-byte
> buffer with a shift-and-OR sequence, and multiplied by a bare 1000.
> Read the register range with sizeof(ck), decode it with
> get_unaligned_be32(), and use HZ_PER_KHZ to convert the kHz register
> value to the Hz value V4L2 DV timings expect. Add the linux/unaligned.h
> and linux/units.h includes these need. While touching this declaration
> block, reorder it per reverse fir-tree.
>
> Signed-off-by: Hermes Wu <[email protected]>
> Signed-off-by: Hans Verkuil <[email protected]>
Patch committed.
Thanks,
Hans Verkuil
drivers/media/i2c/it6625.c | 16 ++++++----------
1 file changed, 6 insertions(+), 10 deletions(-)
---
diff --git a/drivers/media/i2c/it6625.c b/drivers/media/i2c/it6625.c
index 4724c27bd8d0..09af11db5aa8 100644
--- a/drivers/media/i2c/it6625.c
+++ b/drivers/media/i2c/it6625.c
@@ -18,6 +18,8 @@
#include <linux/slab.h>
#include <linux/time64.h>
#include <linux/timer.h>
+#include <linux/unaligned.h>
+#include <linux/units.h>
#include <linux/v4l2-dv-timings.h>
#include <linux/videodev2.h>
#include <linux/workqueue.h>
@@ -636,28 +638,22 @@ static int get_audio_sampling_rate(struct it6625 *it6625)
static u64 it6625_get_pclk(struct it6625 *it6625)
{
- u32 pclk;
u8 ck[4];
+ u32 pclk;
int ret;
- ret = it6625_read_bytes(it6625, REG_VID_PCLK, ck, 4);
+ ret = it6625_read_bytes(it6625, REG_VID_PCLK, ck, sizeof(ck));
if (ret < 0) {
dev_err(it6625->dev, "failed to read pixel clock");
return 0;
}
- pclk = ck[0];
- pclk <<= 8;
- pclk |= ck[1];
- pclk <<= 8;
- pclk |= ck[2];
- pclk <<= 8;
- pclk |= ck[3];
+ pclk = get_unaligned_be32(ck);
v4l2_dbg(1, debug, &it6625->sd, "%s: pclk=%u (%08x)",
__func__, pclk, pclk);
- return (u64)pclk * 1000;
+ return (u64)pclk * HZ_PER_KHZ;
}
static int it6625_read_edid(struct it6625 *it6625, u8 *edid, int start_block,
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