On Thu Sep 24 20:00:54 2026 +0530, Vikash Garodia wrote:
> When video power domain is switched from software-controlled mode to
> hardware-controlled mode, the core may be powered down without the AHB
> bridge going through the required reset sequence. This may leave the
> bridge FIFO in a stale state.
> Reset the CPU-to-VPU AHB bridge before switching the power domain to
> hardware-controlled mode. This ensures that the bridge FIFO are in
> reset state before going for mode switch.
>
> Reported-by: Birk Skyum <[email protected]>
> Link: https://lore.kernel.org/all/[email protected]
> Fixes: 95a337f92f0a ("media: iris: switch to hardware mode after firmware
> boot")
> Cc: [email protected]
> Co-developed-by: Renjiang Han <[email protected]>
> Signed-off-by: Renjiang Han <[email protected]>
> Signed-off-by: Vikash Garodia <[email protected]>
> Reviewed-by: Vishnu Reddy <[email protected]>
> Tested-by: Birk Skyum <[email protected]> # Lenovo Yoga Slim 7x
> Signed-off-by: Bryan O'Donoghue <[email protected]>
Patch committed.
Thanks,
Bryan O'Donoghue
drivers/media/platform/qcom/iris/iris_vpu_common.c | 5 +++++
1 file changed, 5 insertions(+)
---
diff --git a/drivers/media/platform/qcom/iris/iris_vpu_common.c
b/drivers/media/platform/qcom/iris/iris_vpu_common.c
index e4847c107709..2ef8004e976e 100644
--- a/drivers/media/platform/qcom/iris/iris_vpu_common.c
+++ b/drivers/media/platform/qcom/iris/iris_vpu_common.c
@@ -311,6 +311,11 @@ err_disable_power:
int iris_vpu_set_hwmode(struct iris_core *core)
{
+ writel(CORE_BRIDGE_SW_RESET | CORE_BRIDGE_HW_RESET_DISABLE,
+ core->reg_base + CPU_CS_AHB_BRIDGE_SYNC_RESET);
+ writel(CORE_BRIDGE_HW_RESET_DISABLE, core->reg_base +
CPU_CS_AHB_BRIDGE_SYNC_RESET);
+ writel(0x0, core->reg_base + CPU_CS_AHB_BRIDGE_SYNC_RESET);
+
return
dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs[IRIS_HW_POWER_DOMAIN],
true);
}
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