On Thu Oct 1 15:45:39 2026 +0300, Antti Laakso wrote:
> Add buttress psys helpers, needed by ipu7 psys driver.
> 
> Assisted-by: LLM
> Signed-off-by: Antti Laakso <[email protected]>
> Signed-off-by: Sakari Ailus <[email protected]>

Patch committed.

Thanks,
Sakari Ailus

 drivers/media/pci/intel/ipu6/ipu6-buttress.c       | 22 ++++++++++++++++++++++
 drivers/media/pci/intel/ipu6/ipu6-buttress.h       |  2 ++
 .../pci/intel/ipu6/ipu6-platform-buttress-regs.h   |  4 ++++
 drivers/media/pci/intel/ipu6/ipu7-platform-regs.h  | 12 ++++++++++++
 4 files changed, 40 insertions(+)

---

diff --git a/drivers/media/pci/intel/ipu6/ipu6-buttress.c 
b/drivers/media/pci/intel/ipu6/ipu6-buttress.c
index 00d504647c29..f1d236054cf7 100644
--- a/drivers/media/pci/intel/ipu6/ipu6-buttress.c
+++ b/drivers/media/pci/intel/ipu6/ipu6-buttress.c
@@ -1055,6 +1055,28 @@ u32 ipu7_buttress_get_isys_freq(struct ipu6_device *isp)
 }
 EXPORT_SYMBOL_NS_GPL(ipu7_buttress_get_isys_freq, "INTEL_IPU6");
 
+/* trigger uc control to wakeup fw */
+void ipu7_buttress_wakeup_psys(const struct ipu6_device *isp)
+{
+       u32 val;
+
+       val = readl(isp->base + IPU7_BUTTRESS_REG_PSYS_UCX_CTRL_STATUS);
+       val |= IPU7_UCX_CTL_WAKEUP;
+       writel(val, isp->base + IPU7_BUTTRESS_REG_PSYS_UCX_CTRL_STATUS);
+}
+EXPORT_SYMBOL_NS_GPL(ipu7_buttress_wakeup_psys, "INTEL_IPU6");
+
+u32 ipu7_buttress_get_psys_freq(struct ipu6_device *isp)
+{
+       u32 val;
+
+       val = readl(isp->base + IPU7_BUTTRESS_REG_PS_WORKPOINT_REQ);
+       val &= IPU7_BUTTRESS_PS_FREQ_CTL_RATIO_MASK;
+
+       return val * IPU7_BUTTRESS_PS_FREQ_RATIO_STEP;
+}
+EXPORT_SYMBOL_NS_GPL(ipu7_buttress_get_psys_freq, "INTEL_IPU6");
+
 static const struct x86_cpu_id ipu7_misc_cfg_exclusion[] = {
        X86_MATCH_VFM_STEPS(INTEL_PANTHERLAKE_L, 0x1, 0x1, 0),
        {},
diff --git a/drivers/media/pci/intel/ipu6/ipu6-buttress.h 
b/drivers/media/pci/intel/ipu6/ipu6-buttress.h
index 79d8f5893686..39c2951c5370 100644
--- a/drivers/media/pci/intel/ipu6/ipu6-buttress.h
+++ b/drivers/media/pci/intel/ipu6/ipu6-buttress.h
@@ -108,4 +108,6 @@ void ipu6_buttress_csi_port_config(struct ipu6_device *isp,
 void ipu6_buttress_restore(struct ipu6_device *isp);
 void ipu7_buttress_wakeup_isys(const struct ipu6_device *isp);
 u32 ipu7_buttress_get_isys_freq(struct ipu6_device *isp);
+void ipu7_buttress_wakeup_psys(const struct ipu6_device *isp);
+u32 ipu7_buttress_get_psys_freq(struct ipu6_device *isp);
 #endif /* IPU6_BUTTRESS_H */
diff --git a/drivers/media/pci/intel/ipu6/ipu6-platform-buttress-regs.h 
b/drivers/media/pci/intel/ipu6/ipu6-platform-buttress-regs.h
index 04d196c49c60..4c4ca95c7d54 100644
--- a/drivers/media/pci/intel/ipu6/ipu6-platform-buttress-regs.h
+++ b/drivers/media/pci/intel/ipu6/ipu6-platform-buttress-regs.h
@@ -237,6 +237,8 @@ enum {
 #define IPU7_BUTTRESS_REG_PB_TIMESTAMP_VALID   0x2038
 #define IPU7_BUTTRESS_REG_IS_WORKPOINT_REQ     0x2104
 #define IPU7_BUTTRESS_REG_PS_WORKPOINT_REQ     0x2100
+#define IPU7_BUTTRESS_REG_PS_WORKPOINT_DOMAIN_REQ      0x2108
+#define IPU7_BUTTRESS_REG_PS_DOMAINS_STATUS    0x2110
 #define IPU7_BUTTRESS_REG_IDLE_WDT             0x218c
 #define IPU7_BUTTRESS_REG_ISYS_UCX_CTRL_STATUS 0x2200
 #define IPU7_BUTTRESS_REG_ISYS_UCX_START_ADDR  0x2204
@@ -280,6 +282,8 @@ enum {
 #define IPU7_FREQ_CTL_CDYN                     0x80
 #define IPU7_FREQ_CTL_CDYN_SHIFT               8
 #define IPU7_BUTTRESS_IS_FREQ_CTL_RATIO_MASK   GENMASK(7, 0)
+#define IPU7_BUTTRESS_PS_FREQ_CTL_RATIO_MASK   GENMASK(7, 0)
+#define IPU7_BUTTRESS_PS_FREQ_RATIO_STEP       25U
 #define IPU7_IS_FREQ_CTL_DEFAULT_RATIO         0x1b
 #define IPU7_PS_FREQ_CTL_DEFAULT_RATIO         0x14
 /* IS: 400MHz, PS: 400MHz */
diff --git a/drivers/media/pci/intel/ipu6/ipu7-platform-regs.h 
b/drivers/media/pci/intel/ipu6/ipu7-platform-regs.h
index 39cd5c0890e5..3493e0efe24d 100644
--- a/drivers/media/pci/intel/ipu6/ipu7-platform-regs.h
+++ b/drivers/media/pci/intel/ipu6/ipu7-platform-regs.h
@@ -4,6 +4,8 @@
 #ifndef IPU7_PLATFORM_REGS_H
 #define IPU7_PLATFORM_REGS_H
 
+#include <linux/bits.h>
+
 #define IPU7_IS_UC_CTRL_BASE                   0x230000
 #define IPU7_ISYS_DMEM_OFFSET                  0x200000
 #define IPU7_PS_UC_CTRL_BASE                   0x130000
@@ -29,4 +31,14 @@
 #define IPU7_TO_SW_IRQ_FW                      BIT(0)
 #define IPU7_REG_PRINTF_AXI_CNTL               0x301c
 
+/* psys subdomain power request positions in PS_WORKPOINT_DOMAIN_REQ */
+enum ipu7_psys_subdomain_pos {
+       IPU7_PSYS_SUBDOMAIN_LB          = 0,
+       IPU7_PSYS_SUBDOMAIN_BB          = 1,
+};
+
+#define IPU7_PSYS_DOMAIN_POWER_MASK            (BIT(IPU7_PSYS_SUBDOMAIN_LB) | \
+                                                BIT(IPU7_PSYS_SUBDOMAIN_BB))
+#define IPU7_PSYS_DOMAIN_POWER_IN_PROGRESS     BIT(31)
+
 #endif
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