This one isn't meant to be complete, it's merely a step into AArch64 direction.
Before this patch, lldb can't even list AArch64 when cross-compiled and started
on FoundationV8 emulator:
error: attach failed: '/usr/sbin/sshd' doesn't contain any 'host' platform
architectures:
(lldb)
The same goes to lldb-gdbserver (e.g. when started for 'ls' command):
LaunchDebugServerProcess: failed to launch executable ls
error: failed to launch 'ls': 'ls' doesn't contain any 'host' platform
architectures:
With this patch applied, "aarch64" is at least listed as platform architecture:
error: attach failed: '/usr/sbin/sshd' doesn't contain any 'host' platform
architectures: aarch64, aarch64
(lldb)
LaunchDebugServerProcess: failed to launch executable ls
error: failed to launch 'ls': 'ls' doesn't contain any 'host' platform
architectures: aarch64, aarch64
http://reviews.llvm.org/D4381
Files:
include/lldb/Core/ArchSpec.h
source/Core/ArchSpec.cpp
Index: include/lldb/Core/ArchSpec.h
===================================================================
--- include/lldb/Core/ArchSpec.h
+++ include/lldb/Core/ArchSpec.h
@@ -64,6 +64,8 @@
eCore_thumbv7m,
eCore_thumbv7em,
eCore_arm_arm64,
+ eCore_arm_armv8,
+ eCore_arm_aarch64,
eCore_mips64,
Index: source/Core/ArchSpec.cpp
===================================================================
--- source/Core/ArchSpec.cpp
+++ source/Core/ArchSpec.cpp
@@ -78,6 +78,8 @@
{ eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb ,
ArchSpec::eCore_thumbv7m , "thumbv7m" },
{ eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb ,
ArchSpec::eCore_thumbv7em , "thumbv7em" },
{ eByteOrderLittle, 8, 4, 4, llvm::Triple::arm64 ,
ArchSpec::eCore_arm_arm64 , "arm64" },
+ { eByteOrderLittle, 8, 4, 4, llvm::Triple::arm64 ,
ArchSpec::eCore_arm_armv8 , "armv8" },
+ { eByteOrderLittle, 8, 4, 4, llvm::Triple::arm64 ,
ArchSpec::eCore_arm_aarch64 , "aarch64" },
{ eByteOrderBig , 8, 4, 4, llvm::Triple::mips64 , ArchSpec::eCore_mips64
, "mips64" },
@@ -188,6 +190,14 @@
{ ArchSpec::eCore_arm_arm64 , llvm::MachO::CPU_TYPE_ARM64 , 0
, UINT32_MAX , SUBTYPE_MASK },
{ ArchSpec::eCore_arm_arm64 , llvm::MachO::CPU_TYPE_ARM64 , 1
, UINT32_MAX , SUBTYPE_MASK },
{ ArchSpec::eCore_arm_arm64 , llvm::MachO::CPU_TYPE_ARM64 , 13
, UINT32_MAX , SUBTYPE_MASK },
+ { ArchSpec::eCore_arm_armv8 , llvm::MachO::CPU_TYPE_ARM64 ,
CPU_ANY, UINT32_MAX , SUBTYPE_MASK },
+ { ArchSpec::eCore_arm_armv8 , llvm::MachO::CPU_TYPE_ARM64 , 0
, UINT32_MAX , SUBTYPE_MASK },
+ { ArchSpec::eCore_arm_armv8 , llvm::MachO::CPU_TYPE_ARM64 , 1
, UINT32_MAX , SUBTYPE_MASK },
+ { ArchSpec::eCore_arm_armv8 , llvm::MachO::CPU_TYPE_ARM64 , 13
, UINT32_MAX , SUBTYPE_MASK },
+ { ArchSpec::eCore_arm_aarch64 , llvm::MachO::CPU_TYPE_ARM64 ,
CPU_ANY, UINT32_MAX , SUBTYPE_MASK },
+ { ArchSpec::eCore_arm_aarch64 , llvm::MachO::CPU_TYPE_ARM64 , 0
, UINT32_MAX , SUBTYPE_MASK },
+ { ArchSpec::eCore_arm_aarch64 , llvm::MachO::CPU_TYPE_ARM64 , 1
, UINT32_MAX , SUBTYPE_MASK },
+ { ArchSpec::eCore_arm_aarch64 , llvm::MachO::CPU_TYPE_ARM64 , 13
, UINT32_MAX , SUBTYPE_MASK },
{ ArchSpec::eCore_thumb , llvm::MachO::CPU_TYPE_ARM , 0
, UINT32_MAX , SUBTYPE_MASK },
{ ArchSpec::eCore_thumbv4t , llvm::MachO::CPU_TYPE_ARM , 5
, UINT32_MAX , SUBTYPE_MASK },
{ ArchSpec::eCore_thumbv5 , llvm::MachO::CPU_TYPE_ARM , 7
, UINT32_MAX , SUBTYPE_MASK },
Index: include/lldb/Core/ArchSpec.h
===================================================================
--- include/lldb/Core/ArchSpec.h
+++ include/lldb/Core/ArchSpec.h
@@ -64,6 +64,8 @@
eCore_thumbv7m,
eCore_thumbv7em,
eCore_arm_arm64,
+ eCore_arm_armv8,
+ eCore_arm_aarch64,
eCore_mips64,
Index: source/Core/ArchSpec.cpp
===================================================================
--- source/Core/ArchSpec.cpp
+++ source/Core/ArchSpec.cpp
@@ -78,6 +78,8 @@
{ eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb , ArchSpec::eCore_thumbv7m , "thumbv7m" },
{ eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb , ArchSpec::eCore_thumbv7em , "thumbv7em" },
{ eByteOrderLittle, 8, 4, 4, llvm::Triple::arm64 , ArchSpec::eCore_arm_arm64 , "arm64" },
+ { eByteOrderLittle, 8, 4, 4, llvm::Triple::arm64 , ArchSpec::eCore_arm_armv8 , "armv8" },
+ { eByteOrderLittle, 8, 4, 4, llvm::Triple::arm64 , ArchSpec::eCore_arm_aarch64 , "aarch64" },
{ eByteOrderBig , 8, 4, 4, llvm::Triple::mips64 , ArchSpec::eCore_mips64 , "mips64" },
@@ -188,6 +190,14 @@
{ ArchSpec::eCore_arm_arm64 , llvm::MachO::CPU_TYPE_ARM64 , 0 , UINT32_MAX , SUBTYPE_MASK },
{ ArchSpec::eCore_arm_arm64 , llvm::MachO::CPU_TYPE_ARM64 , 1 , UINT32_MAX , SUBTYPE_MASK },
{ ArchSpec::eCore_arm_arm64 , llvm::MachO::CPU_TYPE_ARM64 , 13 , UINT32_MAX , SUBTYPE_MASK },
+ { ArchSpec::eCore_arm_armv8 , llvm::MachO::CPU_TYPE_ARM64 , CPU_ANY, UINT32_MAX , SUBTYPE_MASK },
+ { ArchSpec::eCore_arm_armv8 , llvm::MachO::CPU_TYPE_ARM64 , 0 , UINT32_MAX , SUBTYPE_MASK },
+ { ArchSpec::eCore_arm_armv8 , llvm::MachO::CPU_TYPE_ARM64 , 1 , UINT32_MAX , SUBTYPE_MASK },
+ { ArchSpec::eCore_arm_armv8 , llvm::MachO::CPU_TYPE_ARM64 , 13 , UINT32_MAX , SUBTYPE_MASK },
+ { ArchSpec::eCore_arm_aarch64 , llvm::MachO::CPU_TYPE_ARM64 , CPU_ANY, UINT32_MAX , SUBTYPE_MASK },
+ { ArchSpec::eCore_arm_aarch64 , llvm::MachO::CPU_TYPE_ARM64 , 0 , UINT32_MAX , SUBTYPE_MASK },
+ { ArchSpec::eCore_arm_aarch64 , llvm::MachO::CPU_TYPE_ARM64 , 1 , UINT32_MAX , SUBTYPE_MASK },
+ { ArchSpec::eCore_arm_aarch64 , llvm::MachO::CPU_TYPE_ARM64 , 13 , UINT32_MAX , SUBTYPE_MASK },
{ ArchSpec::eCore_thumb , llvm::MachO::CPU_TYPE_ARM , 0 , UINT32_MAX , SUBTYPE_MASK },
{ ArchSpec::eCore_thumbv4t , llvm::MachO::CPU_TYPE_ARM , 5 , UINT32_MAX , SUBTYPE_MASK },
{ ArchSpec::eCore_thumbv5 , llvm::MachO::CPU_TYPE_ARM , 7 , UINT32_MAX , SUBTYPE_MASK },
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