Hi Tamas, sorry for that last email being a mess, I was doing something else while writing it and only saw how unclear it was after I sent it. You understood everything I was trying to say.
I looked at the AAPCS64 again. It says v8-v15 are callee saved, but says, "Additionally, only the bottom 64-bits of each value stored in v8-v15 need to be preserved; it is the responsibility of the caller to preserve larger values." so we're never going to have a full 128-bit value that we can get off the stack (for targets following this ABI). DWARF can get away with only defining register numbers for v0-v31 because their use in DWARF always includes a byte size. Having lldb register numbers and using that numbering scheme instead of DWARF is an interesting one. It looks like all of the arm64 targets are using the definitions from Plugins/Process/Utility/RegisterInfos_arm64.h. It also only defines v0-v31 but the x86_64 RegisterInfos file defines pseudo registers ("eax") which are a subset of real registers ("rax") - maybe we could do something like that. I'm looking at this right now, but fwiw I wrote a small C program that uses enough fp registers that the compiler will spill all of the preserved registers (d8-d15) when I compile it with clang and -Os. I'll use this for testing
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