jasonmolenda created this revision.
jasonmolenda added reviewers: labath, tberghammer.
jasonmolenda added a subscriber: lldb-commits.
jasonmolenda set the repository for this revision to rL LLVM.
This is a minor change and maybe more of a personal preference, but
UnwindAssemblyInstEmulation marks registers that have been restored to their
original values as "IsSame" - which is equivalent to the UnwindPlan not
mentioning a location for the register at all. When I look at an unwind plan
while a function is executing it's epilogue, the output looks like
row[14]: 520: CFA=sp+320 => x8=[CFA-240] x19= <same> x20= <same> x21= <same>
x22= <same> x23=[CFA-56] x24=[CFA-64] x25=[CFA-72] x26=[CFA-80] x27=[CFA-88]
x28=[CFA-96] fp= <same> lr= <same>
row[15]: 524: CFA=sp+320 => x8=[CFA-240] x19= <same> x20= <same> x21= <same>
x22= <same> x23= <same> x24= <same> x25=[CFA-72] x26=[CFA-80] x27=[CFA-88]
x28=[CFA-96] fp= <same> lr= <same>
row[16]: 528: CFA=sp+320 => x8=[CFA-240] x19= <same> x20= <same> x21= <same>
x22= <same> x23= <same> x24= <same> x25= <same> x26= <same> x27=[CFA-88]
x28=[CFA-96] fp= <same> lr= <same>
row[17]: 532: CFA=sp +0 => x8=[CFA-240] x19= <same> x20= <same> x21= <same>
x22= <same> x23= <same> x24= <same> x25= <same> x26= <same> x27= <same> x28=
<same> fp= <same> lr= <same>
etc. If we remove the registers from the row, the unwind dump will read like
row[14]: 516: CFA=sp+96 => x8=[CFA-240] x21=[CFA-40] x22=[CFA-48] x23=[CFA-56]
x24=[CFA-64] x25=[CFA-72] x26=[CFA-80] x27=[CFA-88] x28=[CFA-96]
row[15]: 520: CFA=sp+96 => x8=[CFA-240] x23=[CFA-56] x24=[CFA-64] x25=[CFA-72]
x26=[CFA-80] x27=[CFA-88] x28=[CFA-96]
row[16]: 524: CFA=sp+96 => x8=[CFA-240] x25=[CFA-72] x26=[CFA-80] x27=[CFA-88]
x28=[CFA-96]
row[17]: 528: CFA=sp+96 => x8=[CFA-240] x27=[CFA-88] x28=[CFA-96]
There's no functional difference between the two (there SHOULD be no functional
difference) - but I think it's a bit easier to read without the IsSame's. Does
anyone care one way or the other?
Repository:
rL LLVM
https://reviews.llvm.org/D26295
Files:
source/Plugins/UnwindAssembly/InstEmulation/UnwindAssemblyInstEmulation.cpp
unittests/UnwindAssembly/InstEmulation/TestArm64InstEmulation.cpp
Index: unittests/UnwindAssembly/InstEmulation/TestArm64InstEmulation.cpp
===================================================================
--- unittests/UnwindAssembly/InstEmulation/TestArm64InstEmulation.cpp
+++ unittests/UnwindAssembly/InstEmulation/TestArm64InstEmulation.cpp
@@ -278,24 +278,16 @@
row_sp = unwind_plan.GetRowForFunctionOffset(32);
EXPECT_EQ(32ull, row_sp->GetOffset());
- // I'd prefer if these restored registers were cleared entirely instead of set
- // to IsSame...
- EXPECT_TRUE(row_sp->GetRegisterInfo(gpr_fp_arm64, regloc));
- EXPECT_TRUE(regloc.IsSame());
-
- EXPECT_TRUE(row_sp->GetRegisterInfo(gpr_lr_arm64, regloc));
- EXPECT_TRUE(regloc.IsSame());
+ EXPECT_FALSE(row_sp->GetRegisterInfo(gpr_fp_arm64, regloc));
+ EXPECT_FALSE(row_sp->GetRegisterInfo(gpr_lr_arm64, regloc));
// 36: CFA=sp+48 => x19= <same> x20= <same> x21=[CFA-40] x22=[CFA-48] fp=
// <same> lr= <same>
row_sp = unwind_plan.GetRowForFunctionOffset(36);
EXPECT_EQ(36ull, row_sp->GetOffset());
- EXPECT_TRUE(row_sp->GetRegisterInfo(gpr_x19_arm64, regloc));
- EXPECT_TRUE(regloc.IsSame());
-
- EXPECT_TRUE(row_sp->GetRegisterInfo(gpr_x20_arm64, regloc));
- EXPECT_TRUE(regloc.IsSame());
+ EXPECT_FALSE(row_sp->GetRegisterInfo(gpr_x19_arm64, regloc));
+ EXPECT_FALSE(row_sp->GetRegisterInfo(gpr_x20_arm64, regloc));
// 40: CFA=sp +0 => x19= <same> x20= <same> x21= <same> x22= <same> fp= <same>
// lr= <same>
@@ -305,11 +297,8 @@
EXPECT_TRUE(row_sp->GetCFAValue().IsRegisterPlusOffset() == true);
EXPECT_EQ(0, row_sp->GetCFAValue().GetOffset());
- EXPECT_TRUE(row_sp->GetRegisterInfo(gpr_x21_arm64, regloc));
- EXPECT_TRUE(regloc.IsSame());
-
- EXPECT_TRUE(row_sp->GetRegisterInfo(gpr_x22_arm64, regloc));
- EXPECT_TRUE(regloc.IsSame());
+ EXPECT_FALSE(row_sp->GetRegisterInfo(gpr_x21_arm64, regloc));
+ EXPECT_FALSE(row_sp->GetRegisterInfo(gpr_x22_arm64, regloc));
}
TEST_F(TestArm64InstEmulation, TestFramelessThreeEpilogueFunction) {
@@ -649,24 +638,14 @@
EXPECT_TRUE(row_sp->GetCFAValue().IsRegisterPlusOffset() == true);
EXPECT_EQ(0, row_sp->GetCFAValue().GetOffset());
- if (row_sp->GetRegisterInfo(fpu_d8_arm64, regloc))
- EXPECT_TRUE(regloc.IsSame());
- if (row_sp->GetRegisterInfo(fpu_d9_arm64, regloc))
- EXPECT_TRUE(regloc.IsSame());
- if (row_sp->GetRegisterInfo(fpu_d10_arm64, regloc))
- EXPECT_TRUE(regloc.IsSame());
- if (row_sp->GetRegisterInfo(fpu_d11_arm64, regloc))
- EXPECT_TRUE(regloc.IsSame());
- if (row_sp->GetRegisterInfo(fpu_d12_arm64, regloc))
- EXPECT_TRUE(regloc.IsSame());
- if (row_sp->GetRegisterInfo(fpu_d13_arm64, regloc))
- EXPECT_TRUE(regloc.IsSame());
- if (row_sp->GetRegisterInfo(fpu_d14_arm64, regloc))
- EXPECT_TRUE(regloc.IsSame());
- if (row_sp->GetRegisterInfo(fpu_d15_arm64, regloc))
- EXPECT_TRUE(regloc.IsSame());
- if (row_sp->GetRegisterInfo(gpr_x27_arm64, regloc))
- EXPECT_TRUE(regloc.IsSame());
- if (row_sp->GetRegisterInfo(gpr_x28_arm64, regloc))
- EXPECT_TRUE(regloc.IsSame());
+ EXPECT_FALSE(row_sp->GetRegisterInfo(fpu_d8_arm64, regloc));
+ EXPECT_FALSE(row_sp->GetRegisterInfo(fpu_d9_arm64, regloc));
+ EXPECT_FALSE(row_sp->GetRegisterInfo(fpu_d10_arm64, regloc));
+ EXPECT_FALSE(row_sp->GetRegisterInfo(fpu_d11_arm64, regloc));
+ EXPECT_FALSE(row_sp->GetRegisterInfo(fpu_d12_arm64, regloc));
+ EXPECT_FALSE(row_sp->GetRegisterInfo(fpu_d13_arm64, regloc));
+ EXPECT_FALSE(row_sp->GetRegisterInfo(fpu_d14_arm64, regloc));
+ EXPECT_FALSE(row_sp->GetRegisterInfo(fpu_d15_arm64, regloc));
+ EXPECT_FALSE(row_sp->GetRegisterInfo(gpr_x27_arm64, regloc));
+ EXPECT_FALSE(row_sp->GetRegisterInfo(gpr_x28_arm64, regloc));
}
Index: source/Plugins/UnwindAssembly/InstEmulation/UnwindAssemblyInstEmulation.cpp
===================================================================
--- source/Plugins/UnwindAssembly/InstEmulation/UnwindAssemblyInstEmulation.cpp
+++ source/Plugins/UnwindAssembly/InstEmulation/UnwindAssemblyInstEmulation.cpp
@@ -602,8 +602,7 @@
case EmulateInstruction::eInfoTypeAddress:
if (m_pushed_regs.find(reg_num) != m_pushed_regs.end() &&
context.info.address == m_pushed_regs[reg_num]) {
- m_curr_row->SetRegisterLocationToSame(reg_num,
- false /*must_replace*/);
+ m_curr_row->RemoveRegisterInfo(reg_num);
m_curr_row_modified = true;
}
break;
@@ -613,8 +612,7 @@
generic_regnum == LLDB_REGNUM_GENERIC_FLAGS) &&
"eInfoTypeISA used for poping a register other the the PC/FLAGS");
if (generic_regnum != LLDB_REGNUM_GENERIC_FLAGS) {
- m_curr_row->SetRegisterLocationToSame(reg_num,
- false /*must_replace*/);
+ m_curr_row->RemoveRegisterInfo(reg_num);
m_curr_row_modified = true;
}
break;
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