https://github.com/DavidSpickett commented:
I'll leave the proper review to the RISC-V interested parties, just some high level points: * The csrs that have names, are all the ones here from the RISC-V standard? Do they include any names allocated for custom extensions or do you plan to do anything like that? (I assume custom extensions can also make use of some csr space, but you could just make people type the generic name for these). * LLDB's design is unfortunately forcing you to enumerate everything up front, I doubt there's much we can do about that without refactoring the others. In some places you might be able to consteveal something, but it probably works out the same if not more in compile time. * You have this riscv-32-dynamic now, is the existing riscv-32 just the dynamic one with no extra registers, can we share the two implementations? * You're treating bare metal core files as if they are Linux, I would like to know if Linux cores themselves work and how far we are from supporting those. This will become a popular use case. You can raise an issue with what you find, I'm not expecting you to do the work. https://github.com/llvm/llvm-project/pull/142932 _______________________________________________ lldb-commits mailing list lldb-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
