https://github.com/hpoussin updated
https://github.com/llvm/llvm-project/pull/147133
From 6296ebd45d3f916bea6bf434c1b5580441f9234a Mon Sep 17 00:00:00 2001
From: Tobias Hieta <tob...@hieta.se>
Date: Tue, 15 Jul 2025 15:59:05 +0200
Subject: [PATCH 01/22] Bump version to 21.1.0-git
---
cmake/Modules/LLVMVersion.cmake | 2 +-
libcxx/include/__config | 2 +-
llvm/utils/gn/secondary/llvm/version.gni | 2 +-
llvm/utils/lit/lit/__init__.py | 2 +-
llvm/utils/mlgo-utils/mlgo/__init__.py | 2 +-
5 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/cmake/Modules/LLVMVersion.cmake b/cmake/Modules/LLVMVersion.cmake
index f14aae172f077..c12240f98e97f 100644
--- a/cmake/Modules/LLVMVersion.cmake
+++ b/cmake/Modules/LLVMVersion.cmake
@@ -4,7 +4,7 @@ if(NOT DEFINED LLVM_VERSION_MAJOR)
set(LLVM_VERSION_MAJOR 21)
endif()
if(NOT DEFINED LLVM_VERSION_MINOR)
- set(LLVM_VERSION_MINOR 0)
+ set(LLVM_VERSION_MINOR 1)
endif()
if(NOT DEFINED LLVM_VERSION_PATCH)
set(LLVM_VERSION_PATCH 0)
diff --git a/libcxx/include/__config b/libcxx/include/__config
index d940461c30234..8f215bbe47928 100644
--- a/libcxx/include/__config
+++ b/libcxx/include/__config
@@ -28,7 +28,7 @@
// _LIBCPP_VERSION represents the version of libc++, which matches the version
of LLVM.
// Given a LLVM release LLVM XX.YY.ZZ (e.g. LLVM 17.0.1 == 17.00.01),
_LIBCPP_VERSION is
// defined to XXYYZZ.
-# define _LIBCPP_VERSION 210000
+# define _LIBCPP_VERSION 210100
# define _LIBCPP_CONCAT_IMPL(_X, _Y) _X##_Y
# define _LIBCPP_CONCAT(_X, _Y) _LIBCPP_CONCAT_IMPL(_X, _Y)
diff --git a/llvm/utils/gn/secondary/llvm/version.gni
b/llvm/utils/gn/secondary/llvm/version.gni
index 2b1a9076afe4a..ece4106de4aca 100644
--- a/llvm/utils/gn/secondary/llvm/version.gni
+++ b/llvm/utils/gn/secondary/llvm/version.gni
@@ -1,4 +1,4 @@
llvm_version_major = 21
-llvm_version_minor = 0
+llvm_version_minor = 1
llvm_version_patch = 0
llvm_version = "$llvm_version_major.$llvm_version_minor.$llvm_version_patch"
diff --git a/llvm/utils/lit/lit/__init__.py b/llvm/utils/lit/lit/__init__.py
index b5aa8edc03dc7..520ff22dc6fb0 100644
--- a/llvm/utils/lit/lit/__init__.py
+++ b/llvm/utils/lit/lit/__init__.py
@@ -2,7 +2,7 @@
__author__ = "Daniel Dunbar"
__email__ = "dan...@minormatter.com"
-__versioninfo__ = (21, 0, 0)
+__versioninfo__ = (21, 1, 0)
__version__ = ".".join(str(v) for v in __versioninfo__) + "dev"
__all__ = []
diff --git a/llvm/utils/mlgo-utils/mlgo/__init__.py
b/llvm/utils/mlgo-utils/mlgo/__init__.py
index d3369abae70b9..03eee0028b3cc 100644
--- a/llvm/utils/mlgo-utils/mlgo/__init__.py
+++ b/llvm/utils/mlgo-utils/mlgo/__init__.py
@@ -4,7 +4,7 @@
from datetime import timezone, datetime
-__versioninfo__ = (20, 0, 0)
+__versioninfo__ = (21, 1, 0)
__version__ = (
".".join(str(v) for v in __versioninfo__)
+ "dev"
From 18624ae54bc979e47ad990721eb20eb9ca982a2f Mon Sep 17 00:00:00 2001
From: Martin Erhart <martin.erh...@sifive.com>
Date: Tue, 15 Jul 2025 14:48:05 +0100
Subject: [PATCH 02/22] [mlir][SliceAnalysis] Fix stack overflow in graph
regions (#139694)
This analysis currently just crashes when applied to a graph region that
has a use-def cycle. This PR fixes that by keeping track of the
operations the DFS has already visited when following use-def edges and
stopping once we visit an operation again.
---
mlir/include/mlir/Analysis/SliceAnalysis.h | 10 ++--
mlir/lib/Analysis/SliceAnalysis.cpp | 65 ++++++++++++++++-----
mlir/test/Dialect/Affine/slicing-utils.mlir | 23 ++++++++
3 files changed, 79 insertions(+), 19 deletions(-)
diff --git a/mlir/include/mlir/Analysis/SliceAnalysis.h
b/mlir/include/mlir/Analysis/SliceAnalysis.h
index d082d2d9f758b..18349d071bb2e 100644
--- a/mlir/include/mlir/Analysis/SliceAnalysis.h
+++ b/mlir/include/mlir/Analysis/SliceAnalysis.h
@@ -65,8 +65,9 @@ using ForwardSliceOptions = SliceOptions;
///
/// The implementation traverses the use chains in postorder traversal for
/// efficiency reasons: if an operation is already in `forwardSlice`, no
-/// need to traverse its uses again. Since use-def chains form a DAG, this
-/// terminates.
+/// need to traverse its uses again. In the presence of use-def cycles in a
+/// graph region, the traversal stops at the first operation that was already
+/// visited (which is not added to the slice anymore).
///
/// Upon return to the root call, `forwardSlice` is filled with a
/// postorder list of uses (i.e. a reverse topological order). To get a proper
@@ -114,8 +115,9 @@ void getForwardSlice(Value root, SetVector<Operation *>
*forwardSlice,
///
/// The implementation traverses the def chains in postorder traversal for
/// efficiency reasons: if an operation is already in `backwardSlice`, no
-/// need to traverse its definitions again. Since useuse-def chains form a DAG,
-/// this terminates.
+/// need to traverse its definitions again. In the presence of use-def cycles
+/// in a graph region, the traversal stops at the first operation that was
+/// already visited (which is not added to the slice anymore).
///
/// Upon return to the root call, `backwardSlice` is filled with a
/// postorder list of defs. This happens to be a topological order, from the
diff --git a/mlir/lib/Analysis/SliceAnalysis.cpp
b/mlir/lib/Analysis/SliceAnalysis.cpp
index 36a9812bd7972..991c71e3f689a 100644
--- a/mlir/lib/Analysis/SliceAnalysis.cpp
+++ b/mlir/lib/Analysis/SliceAnalysis.cpp
@@ -26,7 +26,8 @@
using namespace mlir;
static void
-getForwardSliceImpl(Operation *op, SetVector<Operation *> *forwardSlice,
+getForwardSliceImpl(Operation *op, DenseSet<Operation *> &visited,
+ SetVector<Operation *> *forwardSlice,
const SliceOptions::TransitiveFilter &filter = nullptr) {
if (!op)
return;
@@ -40,20 +41,41 @@ getForwardSliceImpl(Operation *op, SetVector<Operation *>
*forwardSlice,
for (Region ®ion : op->getRegions())
for (Block &block : region)
for (Operation &blockOp : block)
- if (forwardSlice->count(&blockOp) == 0)
- getForwardSliceImpl(&blockOp, forwardSlice, filter);
- for (Value result : op->getResults()) {
- for (Operation *userOp : result.getUsers())
- if (forwardSlice->count(userOp) == 0)
- getForwardSliceImpl(userOp, forwardSlice, filter);
- }
+ if (forwardSlice->count(&blockOp) == 0) {
+ // We don't have to check if the 'blockOp' is already visited because
+ // there cannot be a traversal path from this nested op to the parent
+ // and thus a cycle cannot be closed here. We still have to mark it
+ // as visited to stop before visiting this operation again if it is
+ // part of a cycle.
+ visited.insert(&blockOp);
+ getForwardSliceImpl(&blockOp, visited, forwardSlice, filter);
+ visited.erase(&blockOp);
+ }
+
+ for (Value result : op->getResults())
+ for (Operation *userOp : result.getUsers()) {
+ // A cycle can only occur within a basic block (not across regions or
+ // basic blocks) because the parent region must be a graph region, graph
+ // regions are restricted to always have 0 or 1 blocks, and there cannot
+ // be a def-use edge from a nested operation to an operation in an
+ // ancestor region. Therefore, we don't have to but may use the same
+ // 'visited' set across regions/blocks as long as we remove operations
+ // from the set again when the DFS traverses back from the leaf to the
+ // root.
+ if (forwardSlice->count(userOp) == 0 && visited.insert(userOp).second)
+ getForwardSliceImpl(userOp, visited, forwardSlice, filter);
+
+ visited.erase(userOp);
+ }
forwardSlice->insert(op);
}
void mlir::getForwardSlice(Operation *op, SetVector<Operation *> *forwardSlice,
const ForwardSliceOptions &options) {
- getForwardSliceImpl(op, forwardSlice, options.filter);
+ DenseSet<Operation *> visited;
+ visited.insert(op);
+ getForwardSliceImpl(op, visited, forwardSlice, options.filter);
if (!options.inclusive) {
// Don't insert the top level operation, we just queried on it and don't
// want it in the results.
@@ -69,8 +91,12 @@ void mlir::getForwardSlice(Operation *op,
SetVector<Operation *> *forwardSlice,
void mlir::getForwardSlice(Value root, SetVector<Operation *> *forwardSlice,
const SliceOptions &options) {
- for (Operation *user : root.getUsers())
- getForwardSliceImpl(user, forwardSlice, options.filter);
+ DenseSet<Operation *> visited;
+ for (Operation *user : root.getUsers()) {
+ visited.insert(user);
+ getForwardSliceImpl(user, visited, forwardSlice, options.filter);
+ visited.erase(user);
+ }
// Reverse to get back the actual topological order.
// std::reverse does not work out of the box on SetVector and I want an
@@ -80,6 +106,7 @@ void mlir::getForwardSlice(Value root, SetVector<Operation
*> *forwardSlice,
}
static LogicalResult getBackwardSliceImpl(Operation *op,
+ DenseSet<Operation *> &visited,
SetVector<Operation *>
*backwardSlice,
const BackwardSliceOptions &options)
{
if (!op || op->hasTrait<OpTrait::IsIsolatedFromAbove>())
@@ -93,8 +120,12 @@ static LogicalResult getBackwardSliceImpl(Operation *op,
auto processValue = [&](Value value) {
if (auto *definingOp = value.getDefiningOp()) {
- if (backwardSlice->count(definingOp) == 0)
- return getBackwardSliceImpl(definingOp, backwardSlice, options);
+ if (backwardSlice->count(definingOp) == 0 &&
+ visited.insert(definingOp).second)
+ return getBackwardSliceImpl(definingOp, visited, backwardSlice,
+ options);
+
+ visited.erase(definingOp);
} else if (auto blockArg = dyn_cast<BlockArgument>(value)) {
if (options.omitBlockArguments)
return success();
@@ -107,7 +138,8 @@ static LogicalResult getBackwardSliceImpl(Operation *op,
if (parentOp && backwardSlice->count(parentOp) == 0) {
if (parentOp->getNumRegions() == 1 &&
llvm::hasSingleElement(parentOp->getRegion(0).getBlocks())) {
- return getBackwardSliceImpl(parentOp, backwardSlice, options);
+ return getBackwardSliceImpl(parentOp, visited, backwardSlice,
+ options);
}
}
} else {
@@ -145,7 +177,10 @@ static LogicalResult getBackwardSliceImpl(Operation *op,
LogicalResult mlir::getBackwardSlice(Operation *op,
SetVector<Operation *> *backwardSlice,
const BackwardSliceOptions &options) {
- LogicalResult result = getBackwardSliceImpl(op, backwardSlice, options);
+ DenseSet<Operation *> visited;
+ visited.insert(op);
+ LogicalResult result =
+ getBackwardSliceImpl(op, visited, backwardSlice, options);
if (!options.inclusive) {
// Don't insert the top level operation, we just queried on it and don't
diff --git a/mlir/test/Dialect/Affine/slicing-utils.mlir
b/mlir/test/Dialect/Affine/slicing-utils.mlir
index 0848a924b9d96..c53667a98cfbe 100644
--- a/mlir/test/Dialect/Affine/slicing-utils.mlir
+++ b/mlir/test/Dialect/Affine/slicing-utils.mlir
@@ -292,3 +292,26 @@ func.func @slicing_test_multiple_return(%arg0: index) ->
(index, index) {
%0:2 = "slicing-test-op"(%arg0, %arg0): (index, index) -> (index, index)
return %0#0, %0#1 : index, index
}
+
+// -----
+
+// FWD-LABEL: graph_region_with_cycle
+// BWD-LABEL: graph_region_with_cycle
+// FWDBWD-LABEL: graph_region_with_cycle
+func.func @graph_region_with_cycle() {
+ test.isolated_graph_region {
+ // FWD: matched: [[V0:%.+]] = "slicing-test-op"([[V1:%.+]]) : (i1) -> i1
forward static slice:
+ // FWD: [[V1]] = "slicing-test-op"([[V0]]) : (i1) -> i1
+ // FWD: matched: [[V1]] = "slicing-test-op"([[V0]]) : (i1) -> i1 forward
static slice:
+ // FWD: [[V0]] = "slicing-test-op"([[V1]]) : (i1) -> i1
+
+ // BWD: matched: [[V0:%.+]] = "slicing-test-op"([[V1:%.+]]) : (i1) -> i1
backward static slice:
+ // BWD: [[V1]] = "slicing-test-op"([[V0]]) : (i1) -> i1
+ // BWD: matched: [[V1]] = "slicing-test-op"([[V0]]) : (i1) -> i1 backward
static slice:
+ // BWD: [[V0]] = "slicing-test-op"([[V1]]) : (i1) -> i1
+ %0 = "slicing-test-op"(%1) : (i1) -> i1
+ %1 = "slicing-test-op"(%0) : (i1) -> i1
+ }
+
+ return
+}
From 588b8130794f7ce53fe30237f6bf5614b7122f45 Mon Sep 17 00:00:00 2001
From: Sander de Smalen <sander.desma...@arm.com>
Date: Tue, 15 Jul 2025 14:53:05 +0100
Subject: [PATCH 03/22] [AArch64] Use correct regclass for spills of ZPR2/ZPR4
(#148806)
Commit a6293228fdd5aba8c04c63f02f3d017443feb3f2 forced the register
class of ZPR[24]StridedOrContiguous for spills/fills of ZPR2 and ZPR4,
but this may result in issues when the regclass for the fill is a
ZPR2/ZPR4 which would allow the register allocator to pick `z1_z2`,
which is not a supported register for ZPR2StridedOrContiguous that only
supports tuples of the form (strided) `z0_z8`, `z1_z9` or (contiguous,
start at multiple of 2) `z0_z1`, `z2_z3`. For spills we could add a new
register class that supports any of the tuple forms, but I've decided
to use two pseudos similar to the fills for consistency.
Fixes https://github.com/llvm/llvm-project/issues/148655
---
.../AArch64/AArch64ExpandPseudoInsts.cpp | 4 ++
llvm/lib/Target/AArch64/AArch64InstrInfo.cpp | 40 ++++++++++++---
.../lib/Target/AArch64/AArch64SVEInstrInfo.td | 18 ++++---
llvm/test/CodeGen/AArch64/spillfill-sve.mir | 49 ++++++++++---------
4 files changed, 73 insertions(+), 38 deletions(-)
diff --git a/llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
b/llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
index 36f3a670808d4..07b36d20b0c6d 100644
--- a/llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
@@ -1591,18 +1591,22 @@ bool AArch64ExpandPseudo::expandMI(MachineBasicBlock
&MBB,
"Non-writeback variants of STGloop / STZGloop should not "
"survive past PrologEpilogInserter.");
case AArch64::STR_ZZZZXI:
+ case AArch64::STR_ZZZZXI_STRIDED_CONTIGUOUS:
return expandSVESpillFill(MBB, MBBI, AArch64::STR_ZXI, 4);
case AArch64::STR_ZZZXI:
return expandSVESpillFill(MBB, MBBI, AArch64::STR_ZXI, 3);
case AArch64::STR_ZZXI:
+ case AArch64::STR_ZZXI_STRIDED_CONTIGUOUS:
return expandSVESpillFill(MBB, MBBI, AArch64::STR_ZXI, 2);
case AArch64::STR_PPXI:
return expandSVESpillFill(MBB, MBBI, AArch64::STR_PXI, 2);
case AArch64::LDR_ZZZZXI:
+ case AArch64::LDR_ZZZZXI_STRIDED_CONTIGUOUS:
return expandSVESpillFill(MBB, MBBI, AArch64::LDR_ZXI, 4);
case AArch64::LDR_ZZZXI:
return expandSVESpillFill(MBB, MBBI, AArch64::LDR_ZXI, 3);
case AArch64::LDR_ZZXI:
+ case AArch64::LDR_ZZXI_STRIDED_CONTIGUOUS:
return expandSVESpillFill(MBB, MBBI, AArch64::LDR_ZXI, 2);
case AArch64::LDR_PPXI:
return expandSVESpillFill(MBB, MBBI, AArch64::LDR_PXI, 2);
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
index c1474773faa76..5420545cc3cec 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
@@ -2482,8 +2482,10 @@ unsigned AArch64InstrInfo::getLoadStoreImmIdx(unsigned
Opc) {
case AArch64::LDR_PXI:
case AArch64::LDR_ZXI:
case AArch64::LDR_ZZXI:
+ case AArch64::LDR_ZZXI_STRIDED_CONTIGUOUS:
case AArch64::LDR_ZZZXI:
case AArch64::LDR_ZZZZXI:
+ case AArch64::LDR_ZZZZXI_STRIDED_CONTIGUOUS:
case AArch64::LDRBBui:
case AArch64::LDRBui:
case AArch64::LDRDui:
@@ -2525,8 +2527,10 @@ unsigned AArch64InstrInfo::getLoadStoreImmIdx(unsigned
Opc) {
case AArch64::STR_PXI:
case AArch64::STR_ZXI:
case AArch64::STR_ZZXI:
+ case AArch64::STR_ZZXI_STRIDED_CONTIGUOUS:
case AArch64::STR_ZZZXI:
case AArch64::STR_ZZZZXI:
+ case AArch64::STR_ZZZZXI_STRIDED_CONTIGUOUS:
case AArch64::STRBBui:
case AArch64::STRBui:
case AArch64::STRDui:
@@ -4318,7 +4322,9 @@ bool AArch64InstrInfo::getMemOpInfo(unsigned Opcode,
TypeSize &Scale,
break;
// SVE
case AArch64::STR_ZZZZXI:
+ case AArch64::STR_ZZZZXI_STRIDED_CONTIGUOUS:
case AArch64::LDR_ZZZZXI:
+ case AArch64::LDR_ZZZZXI_STRIDED_CONTIGUOUS:
Scale = TypeSize::getScalable(16);
Width = TypeSize::getScalable(16 * 4);
MinOffset = -256;
@@ -4332,7 +4338,9 @@ bool AArch64InstrInfo::getMemOpInfo(unsigned Opcode,
TypeSize &Scale,
MaxOffset = 253;
break;
case AArch64::STR_ZZXI:
+ case AArch64::STR_ZZXI_STRIDED_CONTIGUOUS:
case AArch64::LDR_ZZXI:
+ case AArch64::LDR_ZZXI_STRIDED_CONTIGUOUS:
Scale = TypeSize::getScalable(16);
Width = TypeSize::getScalable(16 * 2);
MinOffset = -256;
@@ -5559,8 +5567,12 @@ void
AArch64InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
assert(Subtarget.hasNEON() && "Unexpected register store without NEON");
Opc = AArch64::ST1Twov2d;
Offset = false;
- } else if (AArch64::ZPR2RegClass.hasSubClassEq(RC) ||
- AArch64::ZPR2StridedOrContiguousRegClass.hasSubClassEq(RC)) {
+ } else if (AArch64::ZPR2StridedOrContiguousRegClass.hasSubClassEq(RC)) {
+ assert(Subtarget.isSVEorStreamingSVEAvailable() &&
+ "Unexpected register store without SVE store instructions");
+ Opc = AArch64::STR_ZZXI_STRIDED_CONTIGUOUS;
+ StackID = TargetStackID::ScalableVector;
+ } else if (AArch64::ZPR2RegClass.hasSubClassEq(RC)) {
assert(Subtarget.isSVEorStreamingSVEAvailable() &&
"Unexpected register store without SVE store instructions");
Opc = AArch64::STR_ZZXI;
@@ -5584,8 +5596,12 @@ void
AArch64InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
assert(Subtarget.hasNEON() && "Unexpected register store without NEON");
Opc = AArch64::ST1Fourv2d;
Offset = false;
- } else if (AArch64::ZPR4RegClass.hasSubClassEq(RC) ||
- AArch64::ZPR4StridedOrContiguousRegClass.hasSubClassEq(RC)) {
+ } else if (AArch64::ZPR4StridedOrContiguousRegClass.hasSubClassEq(RC)) {
+ assert(Subtarget.isSVEorStreamingSVEAvailable() &&
+ "Unexpected register store without SVE store instructions");
+ Opc = AArch64::STR_ZZZZXI_STRIDED_CONTIGUOUS;
+ StackID = TargetStackID::ScalableVector;
+ } else if (AArch64::ZPR4RegClass.hasSubClassEq(RC)) {
assert(Subtarget.isSVEorStreamingSVEAvailable() &&
"Unexpected register store without SVE store instructions");
Opc = AArch64::STR_ZZZZXI;
@@ -5736,8 +5752,12 @@ void AArch64InstrInfo::loadRegFromStackSlot(
assert(Subtarget.hasNEON() && "Unexpected register load without NEON");
Opc = AArch64::LD1Twov2d;
Offset = false;
- } else if (AArch64::ZPR2RegClass.hasSubClassEq(RC) ||
- AArch64::ZPR2StridedOrContiguousRegClass.hasSubClassEq(RC)) {
+ } else if (AArch64::ZPR2StridedOrContiguousRegClass.hasSubClassEq(RC)) {
+ assert(Subtarget.isSVEorStreamingSVEAvailable() &&
+ "Unexpected register load without SVE load instructions");
+ Opc = AArch64::LDR_ZZXI_STRIDED_CONTIGUOUS;
+ StackID = TargetStackID::ScalableVector;
+ } else if (AArch64::ZPR2RegClass.hasSubClassEq(RC)) {
assert(Subtarget.isSVEorStreamingSVEAvailable() &&
"Unexpected register load without SVE load instructions");
Opc = AArch64::LDR_ZZXI;
@@ -5761,8 +5781,12 @@ void AArch64InstrInfo::loadRegFromStackSlot(
assert(Subtarget.hasNEON() && "Unexpected register load without NEON");
Opc = AArch64::LD1Fourv2d;
Offset = false;
- } else if (AArch64::ZPR4RegClass.hasSubClassEq(RC) ||
- AArch64::ZPR4StridedOrContiguousRegClass.hasSubClassEq(RC)) {
+ } else if (AArch64::ZPR4StridedOrContiguousRegClass.hasSubClassEq(RC)) {
+ assert(Subtarget.isSVEorStreamingSVEAvailable() &&
+ "Unexpected register load without SVE load instructions");
+ Opc = AArch64::LDR_ZZZZXI_STRIDED_CONTIGUOUS;
+ StackID = TargetStackID::ScalableVector;
+ } else if (AArch64::ZPR4RegClass.hasSubClassEq(RC)) {
assert(Subtarget.isSVEorStreamingSVEAvailable() &&
"Unexpected register load without SVE load instructions");
Opc = AArch64::LDR_ZZZZXI;
diff --git a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
index eddb96979f7b8..0c4b4f4c3ed88 100644
--- a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
@@ -2625,16 +2625,22 @@ let Predicates = [HasSVE_or_SME] in {
// These get expanded to individual LDR_ZXI/STR_ZXI instructions in
// AArch64ExpandPseudoInsts.
let mayLoad = 1, hasSideEffects = 0 in {
- def LDR_ZZXI : Pseudo<(outs ZZ_b_strided_and_contiguous:$Zd), (ins
GPR64sp:$sp, simm4s1:$offset),[]>, Sched<[]>;
+ def LDR_ZZXI_STRIDED_CONTIGUOUS : Pseudo<(outs
ZZ_b_strided_and_contiguous:$Zd), (ins GPR64sp:$sp, simm4s1:$offset),[]>,
Sched<[]>;
+ def LDR_ZZZZXI_STRIDED_CONTIGUOUS : Pseudo<(outs
ZZZZ_b_strided_and_contiguous:$Zd), (ins GPR64sp:$sp, simm4s1:$offset),[]>,
Sched<[]>;
+
+ def LDR_ZZXI : Pseudo<(outs ZZ_b:$Zd), (ins GPR64sp:$sp,
simm4s1:$offset),[]>, Sched<[]>;
def LDR_ZZZXI : Pseudo<(outs ZZZ_b:$Zd), (ins GPR64sp:$sp,
simm4s1:$offset),[]>, Sched<[]>;
- def LDR_ZZZZXI : Pseudo<(outs ZZZZ_b_strided_and_contiguous:$Zd), (ins
GPR64sp:$sp, simm4s1:$offset),[]>, Sched<[]>;
- def LDR_PPXI : Pseudo<(outs PPR2:$pp), (ins GPR64sp:$sp,
simm4s1:$offset),[]>, Sched<[]>;
+ def LDR_ZZZZXI : Pseudo<(outs ZZZZ_b:$Zd), (ins GPR64sp:$sp,
simm4s1:$offset),[]>, Sched<[]>;
+ def LDR_PPXI : Pseudo<(outs PPR2:$pp), (ins GPR64sp:$sp,
simm4s1:$offset),[]>, Sched<[]>;
}
let mayStore = 1, hasSideEffects = 0 in {
- def STR_ZZXI : Pseudo<(outs), (ins ZZ_b_strided_and_contiguous:$Zs,
GPR64sp:$sp, simm4s1:$offset),[]>, Sched<[]>;
+ def STR_ZZXI_STRIDED_CONTIGUOUS : Pseudo<(outs), (ins
ZZ_b_strided_and_contiguous:$Zs, GPR64sp:$sp, simm4s1:$offset),[]>, Sched<[]>;
+ def STR_ZZZZXI_STRIDED_CONTIGUOUS : Pseudo<(outs), (ins
ZZZZ_b_strided_and_contiguous:$Zs, GPR64sp:$sp, simm4s1:$offset),[]>, Sched<[]>;
+
+ def STR_ZZXI : Pseudo<(outs), (ins ZZ_b:$Zs, GPR64sp:$sp,
simm4s1:$offset),[]>, Sched<[]>;
def STR_ZZZXI : Pseudo<(outs), (ins ZZZ_b:$Zs, GPR64sp:$sp,
simm4s1:$offset),[]>, Sched<[]>;
- def STR_ZZZZXI : Pseudo<(outs), (ins ZZZZ_b_strided_and_contiguous:$Zs,
GPR64sp:$sp, simm4s1:$offset),[]>, Sched<[]>;
- def STR_PPXI : Pseudo<(outs), (ins PPR2:$pp, GPR64sp:$sp,
simm4s1:$offset),[]>, Sched<[]>;
+ def STR_ZZZZXI : Pseudo<(outs), (ins ZZZZ_b:$Zs, GPR64sp:$sp,
simm4s1:$offset),[]>, Sched<[]>;
+ def STR_PPXI : Pseudo<(outs), (ins PPR2:$pp, GPR64sp:$sp,
simm4s1:$offset),[]>, Sched<[]>;
}
let AddedComplexity = 1 in {
diff --git a/llvm/test/CodeGen/AArch64/spillfill-sve.mir
b/llvm/test/CodeGen/AArch64/spillfill-sve.mir
index 83c9b73c57570..2b16dd0f29ecc 100644
--- a/llvm/test/CodeGen/AArch64/spillfill-sve.mir
+++ b/llvm/test/CodeGen/AArch64/spillfill-sve.mir
@@ -1,5 +1,5 @@
-# RUN: llc -mtriple=aarch64-linux-gnu -run-pass=greedy %s -o - | FileCheck %s
-# RUN: llc -mtriple=aarch64-linux-gnu -start-before=greedy
-stop-after=aarch64-expand-pseudo -verify-machineinstrs %s -o - | FileCheck %s
--check-prefix=EXPAND
+# RUN: llc -mtriple=aarch64-linux-gnu -run-pass=greedy
-aarch64-stack-hazard-size=0 %s -o - | FileCheck %s
+# RUN: llc -mtriple=aarch64-linux-gnu -start-before=greedy
-stop-after=aarch64-expand-pseudo -verify-machineinstrs
-aarch64-stack-hazard-size=0 %s -o - | FileCheck %s --check-prefix=EXPAND
--- |
; ModuleID = '<stdin>'
source_filename = "<stdin>"
@@ -14,13 +14,14 @@
define aarch64_sve_vector_pcs void
@spills_fills_stack_id_virtreg_ppr_to_pnr() #1 { entry: unreachable }
define aarch64_sve_vector_pcs void @spills_fills_stack_id_zpr() #0 { entry:
unreachable }
define aarch64_sve_vector_pcs void @spills_fills_stack_id_zpr2() #0 { entry:
unreachable }
- define aarch64_sve_vector_pcs void @spills_fills_stack_id_zpr2strided() #0 {
entry: unreachable }
+ define aarch64_sve_vector_pcs void @spills_fills_stack_id_zpr2strided() #2 {
entry: unreachable }
define aarch64_sve_vector_pcs void @spills_fills_stack_id_zpr3() #0 { entry:
unreachable }
define aarch64_sve_vector_pcs void @spills_fills_stack_id_zpr4() #0 { entry:
unreachable }
- define aarch64_sve_vector_pcs void @spills_fills_stack_id_zpr4strided() #0 {
entry: unreachable }
+ define aarch64_sve_vector_pcs void @spills_fills_stack_id_zpr4strided() #2 {
entry: unreachable }
attributes #0 = { nounwind "target-features"="+sve" }
attributes #1 = { nounwind "target-features"="+sve2p1" }
+ attributes #2 = { nounwind "target-features"="+sve,+sme2"
"aarch64_pstate_sm_enabled" }
...
---
@@ -318,10 +319,10 @@ registers:
- { id: 0, class: zpr2 }
stack:
liveins:
- - { reg: '$z0_z1', virtual-reg: '%0' }
+ - { reg: '$z1_z2', virtual-reg: '%0' }
body: |
bb.0.entry:
- liveins: $z0_z1
+ liveins: $z1_z2
; CHECK-LABEL: name: spills_fills_stack_id_zpr2
; CHECK: stack:
@@ -329,12 +330,12 @@ body: |
; CHECK-NEXT: stack-id: scalable-vector
; EXPAND-LABEL: name: spills_fills_stack_id_zpr2
- ; EXPAND: STR_ZXI $z0, $sp, 0
- ; EXPAND: STR_ZXI $z1, $sp, 1
- ; EXPAND: $z0 = LDR_ZXI $sp, 0
- ; EXPAND: $z1 = LDR_ZXI $sp, 1
+ ; EXPAND: STR_ZXI $z1, $sp, 0
+ ; EXPAND: STR_ZXI $z2, $sp, 1
+ ; EXPAND: $z1 = LDR_ZXI $sp, 0
+ ; EXPAND: $z2 = LDR_ZXI $sp, 1
- %0:zpr2 = COPY $z0_z1
+ %0:zpr2 = COPY $z1_z2
$z0_z1_z2_z3 = IMPLICIT_DEF
$z4_z5_z6_z7 = IMPLICIT_DEF
@@ -345,7 +346,7 @@ body: |
$z24_z25_z26_z27 = IMPLICIT_DEF
$z28_z29_z30_z31 = IMPLICIT_DEF
- $z0_z1 = COPY %0
+ $z1_z2 = COPY %0
RET_ReallyLR
...
---
@@ -439,10 +440,10 @@ registers:
- { id: 0, class: zpr4 }
stack:
liveins:
- - { reg: '$z0_z1_z2_z3', virtual-reg: '%0' }
+ - { reg: '$z1_z2_z3_z4', virtual-reg: '%0' }
body: |
bb.0.entry:
- liveins: $z0_z1_z2_z3
+ liveins: $z1_z2_z3_z4
; CHECK-LABEL: name: spills_fills_stack_id_zpr4
; CHECK: stack:
@@ -450,16 +451,16 @@ body: |
; CHECK-NEXT: stack-id: scalable-vector
; EXPAND-LABEL: name: spills_fills_stack_id_zpr4
- ; EXPAND: STR_ZXI $z0, $sp, 0
- ; EXPAND: STR_ZXI $z1, $sp, 1
- ; EXPAND: STR_ZXI $z2, $sp, 2
- ; EXPAND: STR_ZXI $z3, $sp, 3
- ; EXPAND: $z0 = LDR_ZXI $sp, 0
- ; EXPAND: $z1 = LDR_ZXI $sp, 1
- ; EXPAND: $z2 = LDR_ZXI $sp, 2
- ; EXPAND: $z3 = LDR_ZXI $sp, 3
+ ; EXPAND: STR_ZXI $z1, $sp, 0
+ ; EXPAND: STR_ZXI $z2, $sp, 1
+ ; EXPAND: STR_ZXI $z3, $sp, 2
+ ; EXPAND: STR_ZXI $z4, $sp, 3
+ ; EXPAND: $z1 = LDR_ZXI $sp, 0
+ ; EXPAND: $z2 = LDR_ZXI $sp, 1
+ ; EXPAND: $z3 = LDR_ZXI $sp, 2
+ ; EXPAND: $z4 = LDR_ZXI $sp, 3
- %0:zpr4 = COPY $z0_z1_z2_z3
+ %0:zpr4 = COPY $z1_z2_z3_z4
$z0_z1_z2_z3 = IMPLICIT_DEF
$z4_z5_z6_z7 = IMPLICIT_DEF
@@ -470,7 +471,7 @@ body: |
$z24_z25_z26_z27 = IMPLICIT_DEF
$z28_z29_z30_z31 = IMPLICIT_DEF
- $z0_z1_z2_z3 = COPY %0
+ $z1_z2_z3_z4 = COPY %0
RET_ReallyLR
...
---
From d1517ec62222584304951fcf63ce35d8fd0942f2 Mon Sep 17 00:00:00 2001
From: Sander de Smalen <sander.desma...@arm.com>
Date: Tue, 15 Jul 2025 14:53:47 +0100
Subject: [PATCH 04/22] [AArch64] Ensure bundle expansion of MOVPRFX gets
correct implicit ops (#148824)
By finalizing the bundle _after_ copying over the implicit-ops, it also
adds any implicit-defs to the BUNDLE.
Fixes https://github.com/llvm/llvm-project/issues/148645
---
.../AArch64/AArch64ExpandPseudoInsts.cpp | 2 +-
.../AArch64/sve-pseudos-expand-undef.mir | 20 ++++++++++++++++---
2 files changed, 18 insertions(+), 4 deletions(-)
diff --git a/llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
b/llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
index 07b36d20b0c6d..7de66ccbf6f29 100644
--- a/llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
@@ -671,8 +671,8 @@ bool AArch64ExpandPseudo::expand_DestructiveOp(
}
if (PRFX) {
- finalizeBundle(MBB, PRFX->getIterator(), MBBI->getIterator());
transferImpOps(MI, PRFX, DOP);
+ finalizeBundle(MBB, PRFX->getIterator(), MBBI->getIterator());
} else
transferImpOps(MI, DOP, DOP);
diff --git a/llvm/test/CodeGen/AArch64/sve-pseudos-expand-undef.mir
b/llvm/test/CodeGen/AArch64/sve-pseudos-expand-undef.mir
index ae70f91a4ec64..a1d615c910792 100644
--- a/llvm/test/CodeGen/AArch64/sve-pseudos-expand-undef.mir
+++ b/llvm/test/CodeGen/AArch64/sve-pseudos-expand-undef.mir
@@ -12,7 +12,7 @@ body: |
bb.0:
liveins: $p0, $z0
- ; CHECK: add_x
+ ; CHECK: name: add_x
; CHECK-NOT: MOVPRFX
; CHECK: $z0 = FADD_ZPmZ_S renamable $p0, killed $z0, renamable $z0
; CHECK-NEXT: RET
@@ -21,22 +21,36 @@ body: |
...
-# CHECK: {{.*}} MSB_ZPmZZ_B {{.*}}
---
name: expand_mls_to_msb
body: |
bb.0:
+ ; CHECK: name: expand_mls_to_msb
+ ; CHECK: {{.*}} MSB_ZPmZZ_B {{.*}}
renamable $p0 = PTRUE_B 31, implicit $vg
renamable $z0 = MLS_ZPZZZ_B_UNDEF killed renamable $p0, killed renamable
$z2, killed renamable $z0, killed renamable $z1
RET_ReallyLR implicit $z0
...
-# CHECK: {{.*}} MAD_ZPmZZ_B {{.*}}
---
name: expand_mla_to_mad
body: |
bb.0:
+ ; CHECK: name: expand_mla_to_mad
+ ; CHECK: {{.*}} MAD_ZPmZZ_B {{.*}}
renamable $p0 = PTRUE_B 31, implicit $vg
renamable $z0 = MLA_ZPZZZ_B_UNDEF killed renamable $p0, killed renamable
$z2, killed renamable $z0, killed renamable $z1
RET_ReallyLR implicit $z0
...
+
+---
+name: expand_transfer_implicit_defs
+body: |
+ bb.0:
+ ; CHECK: name: expand_transfer_implicit_defs
+ ; CHECK: BUNDLE
+ ; CHECK-SAME: implicit-def $z0_z1_z2_z3
+ liveins: $z1, $z2, $p0
+ renamable $z0 = FADD_ZPZZ_D_UNDEF killed $p0, killed $z1, killed $z2,
implicit-def $z0_z1_z2_z3
+ RET_ReallyLR implicit $z0_z1_z2_z3
+...
From 7d803c868ab96dabbd4cb47d0b3e60a78057e1b0 Mon Sep 17 00:00:00 2001
From: Sjoerd Meijer <smei...@nvidia.com>
Date: Tue, 15 Jul 2025 14:59:18 +0100
Subject: [PATCH 05/22] [AArch64] Set the cache line size to 64 for the V2 and
V3. (#148213)
This sets the cache line size to 64 for the Neoverse V2 and V3. I've
tested this with loop-interchange: it doesn't result in extra
compile-times, but it does enable a lot more interchange.
---
llvm/lib/Target/AArch64/AArch64Subtarget.cpp | 1 +
1 file changed, 1 insertion(+)
diff --git a/llvm/lib/Target/AArch64/AArch64Subtarget.cpp
b/llvm/lib/Target/AArch64/AArch64Subtarget.cpp
index 0956823346795..2409cc862f21c 100644
--- a/llvm/lib/Target/AArch64/AArch64Subtarget.cpp
+++ b/llvm/lib/Target/AArch64/AArch64Subtarget.cpp
@@ -270,6 +270,7 @@ void AArch64Subtarget::initializeProperties(bool
HasMinSize) {
break;
case NeoverseV2:
case NeoverseV3:
+ CacheLineSize = 64;
EpilogueVectorizationMinVF = 8;
MaxInterleaveFactor = 4;
ScatterOverhead = 13;
From a0895b4581bac8634596263b42d49c7f2e2d957f Mon Sep 17 00:00:00 2001
From: Krzysztof Parzyszek <krzysztof.parzys...@amd.com>
Date: Tue, 15 Jul 2025 09:00:15 -0500
Subject: [PATCH 06/22] [Frontend][OpenMP] Move isPrivatizingClause to OMP.h,
NFC (#148644)
---
.../Frontend/OpenMP/ConstructDecompositionT.h | 18 +-----------------
llvm/include/llvm/Frontend/OpenMP/OMP.h | 16 ++++++++++++++++
2 files changed, 17 insertions(+), 17 deletions(-)
diff --git a/llvm/include/llvm/Frontend/OpenMP/ConstructDecompositionT.h
b/llvm/include/llvm/Frontend/OpenMP/ConstructDecompositionT.h
index cdc80c88b7425..611bfe3f8aced 100644
--- a/llvm/include/llvm/Frontend/OpenMP/ConstructDecompositionT.h
+++ b/llvm/include/llvm/Frontend/OpenMP/ConstructDecompositionT.h
@@ -795,25 +795,9 @@ bool ConstructDecompositionT<C, H>::applyClause(
// assigned to which leaf constructs.
// [5.2:340:33]
- auto canMakePrivateCopy = [](llvm::omp::Clause id) {
- switch (id) {
- // Clauses with "privatization" property:
- case llvm::omp::Clause::OMPC_firstprivate:
- case llvm::omp::Clause::OMPC_in_reduction:
- case llvm::omp::Clause::OMPC_lastprivate:
- case llvm::omp::Clause::OMPC_linear:
- case llvm::omp::Clause::OMPC_private:
- case llvm::omp::Clause::OMPC_reduction:
- case llvm::omp::Clause::OMPC_task_reduction:
- return true;
- default:
- return false;
- }
- };
-
bool applied = applyIf(node, [&](const auto &leaf) {
return llvm::any_of(leaf.clauses, [&](const ClauseTy *n) {
- return canMakePrivateCopy(n->id);
+ return llvm::omp::isPrivatizingClause(n->id);
});
});
diff --git a/llvm/include/llvm/Frontend/OpenMP/OMP.h
b/llvm/include/llvm/Frontend/OpenMP/OMP.h
index 35dafc6d246f0..d44c33301bde7 100644
--- a/llvm/include/llvm/Frontend/OpenMP/OMP.h
+++ b/llvm/include/llvm/Frontend/OpenMP/OMP.h
@@ -48,6 +48,22 @@ static constexpr inline bool canHaveIterator(Clause C) {
}
}
+// Can clause C create a private copy of a variable.
+static constexpr inline bool isPrivatizingClause(Clause C) {
+ switch (C) {
+ case OMPC_firstprivate:
+ case OMPC_in_reduction:
+ case OMPC_lastprivate:
+ case OMPC_linear:
+ case OMPC_private:
+ case OMPC_reduction:
+ case OMPC_task_reduction:
+ return true;
+ default:
+ return false;
+ }
+}
+
static constexpr unsigned FallbackVersion = 52;
LLVM_ABI ArrayRef<unsigned> getOpenMPVersions();
From 49722f1df1ef62de3b1b671c2d4a11c08be11774 Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.top...@sifive.com>
Date: Tue, 15 Jul 2025 10:49:23 -0700
Subject: [PATCH 07/22] [RISCV] Remove incorrect and untested FrameIndex
support from SelectAddrRegImm9. (#148779)
To fold a FrameIndex, we need to teach eliminateFrameIndex to respect
the uimm9 range.
(cherry picked from commit 63d099af146a19bc8fd5a791d6184125e6cc42e7)
---
llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
index 666c76b21e631..880e6b0d48892 100644
--- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
@@ -2936,8 +2936,8 @@ bool RISCVDAGToDAGISel::SelectAddrRegImm(SDValue Addr,
SDValue &Base,
/// Similar to SelectAddrRegImm, except that the offset is restricted to uimm9.
bool RISCVDAGToDAGISel::SelectAddrRegImm9(SDValue Addr, SDValue &Base,
SDValue &Offset) {
- if (SelectAddrFrameIndex(Addr, Base, Offset))
- return true;
+ // FIXME: Support FrameIndex. Need to teach eliminateFrameIndex that only
+ // a 9-bit immediate can be folded.
SDLoc DL(Addr);
MVT VT = Addr.getSimpleValueType();
@@ -2947,8 +2947,8 @@ bool RISCVDAGToDAGISel::SelectAddrRegImm9(SDValue Addr,
SDValue &Base,
if (isUInt<9>(CVal)) {
Base = Addr.getOperand(0);
- if (auto *FIN = dyn_cast<FrameIndexSDNode>(Base))
- Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), VT);
+ // FIXME: Support FrameIndex. Need to teach eliminateFrameIndex that only
+ // a 9-bit immediate can be folded.
Offset = CurDAG->getSignedTargetConstant(CVal, DL, VT);
return true;
}
From b71c9a43664101ff46fa0a46041a238d369a7784 Mon Sep 17 00:00:00 2001
From: Sudharsan Veeravalli <quic_...@quicinc.com>
Date: Wed, 16 Jul 2025 00:31:33 +0530
Subject: [PATCH 08/22] [RISCV] Fix issues in ORI to QC.INSBI transformation
(#148809)
The transformation done in #147349 was incorrect since we were not
passing the input node of the `OR` instruction to the `QC.INSBI`
instruction leading to the generated instruction doing the wrong thing.
In order to do this we first needed to add the output register to
`QC.INSBI` as being both an input and output.
The code produced after the above fix will need a copy (mv) to preserve
the register input to the OR instruction if it has more than one use
making the transformation net neutral ( `6-byte QC.E.ORI/ORAI` vs
`2-byte C.MV + 4-byte QC.INSB`I). Avoid doing the transformation if
there is more than one use of the input register to the OR instruction.
(cherry picked from commit d67d91a9906366585162cebf292f923a3f28c8a6)
---
llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp | 10 +++-
llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td | 5 +-
.../test/CodeGen/RISCV/xqcibm-cto-clo-brev.ll | 1 +
llvm/test/CodeGen/RISCV/xqcibm-insert.ll | 53 +++++++++++++++++++
4 files changed, 65 insertions(+), 4 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
index 880e6b0d48892..186191abe12a2 100644
--- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
@@ -689,10 +689,16 @@ bool
RISCVDAGToDAGISel::trySignedBitfieldInsertInMask(SDNode *Node) {
if (!isShiftedMask_32(C1) || isInt<12>(C1))
return false;
+ // INSBI will clobber the input register in N0. Bail out if we need a copy to
+ // preserve this value.
+ SDValue N0 = Node->getOperand(0);
+ if (!N0.hasOneUse())
+ return false;
+
// If C1 is a shifted mask (but can't be formed as an ORI),
// use a bitfield insert of -1.
// Transform (or x, C1)
- // -> (qc.insbi x, width, shift)
+ // -> (qc.insbi x, -1, width, shift)
const unsigned Leading = llvm::countl_zero((uint32_t)C1);
const unsigned Trailing = llvm::countr_zero((uint32_t)C1);
const unsigned Width = 32 - Leading - Trailing;
@@ -705,7 +711,7 @@ bool
RISCVDAGToDAGISel::trySignedBitfieldInsertInMask(SDNode *Node) {
SDLoc DL(Node);
MVT VT = Node->getSimpleValueType(0);
- SDValue Ops[] = {CurDAG->getSignedTargetConstant(-1, DL, VT),
+ SDValue Ops[] = {N0, CurDAG->getSignedTargetConstant(-1, DL, VT),
CurDAG->getTargetConstant(Width, DL, VT),
CurDAG->getTargetConstant(Trailing, DL, VT)};
SDNode *BitIns = CurDAG->getMachineNode(RISCV::QC_INSBI, DL, VT, Ops);
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
b/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
index 26bb1e8d17857..c7cb6e237aeac 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
@@ -845,10 +845,11 @@ let Predicates = [HasVendorXqcibi, IsRV32] in {
let Predicates = [HasVendorXqcibm, IsRV32] in {
let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
def QC_INSBRI : QCIRVInstRI<0b1, simm11, "qc.insbri">;
- def QC_INSBI : RVInstIBase<0b001, OPC_CUSTOM_0, (outs GPRNoX0:$rd),
- (ins simm5:$imm5, uimm5_plus1:$width,
+ def QC_INSBI : RVInstIBase<0b001, OPC_CUSTOM_0, (outs GPRNoX0:$rd_wb),
+ (ins GPRNoX0:$rd, simm5:$imm5, uimm5_plus1:$width,
uimm5:$shamt), "qc.insbi",
"$rd, $imm5, $width, $shamt"> {
+ let Constraints = "$rd = $rd_wb";
bits<5> imm5;
bits<5> shamt;
bits<5> width;
diff --git a/llvm/test/CodeGen/RISCV/xqcibm-cto-clo-brev.ll
b/llvm/test/CodeGen/RISCV/xqcibm-cto-clo-brev.ll
index f227fa9aa423d..2fa06517508ce 100644
--- a/llvm/test/CodeGen/RISCV/xqcibm-cto-clo-brev.ll
+++ b/llvm/test/CodeGen/RISCV/xqcibm-cto-clo-brev.ll
@@ -105,6 +105,7 @@ define i16 @test_cttz_i16(i16 %a) nounwind {
;
; RV32ZBBXQCIBM-LABEL: test_cttz_i16:
; RV32ZBBXQCIBM: # %bb.0:
+; RV32ZBBXQCIBM-NEXT: not a0, a0
; RV32ZBBXQCIBM-NEXT: qc.insbi a0, -1, 1, 16
; RV32ZBBXQCIBM-NEXT: ctz a0, a0
; RV32ZBBXQCIBM-NEXT: ret
diff --git a/llvm/test/CodeGen/RISCV/xqcibm-insert.ll
b/llvm/test/CodeGen/RISCV/xqcibm-insert.ll
index 6b7f9ae856625..88054a691bad1 100644
--- a/llvm/test/CodeGen/RISCV/xqcibm-insert.ll
+++ b/llvm/test/CodeGen/RISCV/xqcibm-insert.ll
@@ -47,6 +47,29 @@ define i32 @test_insbi_mask(i32 %a) nounwind {
ret i32 %or
}
+define i32 @test_insbi_mask_mv(i32 %a, i32 %b) nounwind {
+; RV32I-LABEL: test_insbi_mask_mv:
+; RV32I: # %bb.0:
+; RV32I-NEXT: lui a0, 16
+; RV32I-NEXT: addi a0, a0, -1
+; RV32I-NEXT: or a0, a1, a0
+; RV32I-NEXT: ret
+;
+; RV32IXQCIBM-LABEL: test_insbi_mask_mv:
+; RV32IXQCIBM: # %bb.0:
+; RV32IXQCIBM-NEXT: mv a0, a1
+; RV32IXQCIBM-NEXT: qc.insbi a0, -1, 16, 0
+; RV32IXQCIBM-NEXT: ret
+;
+; RV32IXQCIBMZBS-LABEL: test_insbi_mask_mv:
+; RV32IXQCIBMZBS: # %bb.0:
+; RV32IXQCIBMZBS-NEXT: mv a0, a1
+; RV32IXQCIBMZBS-NEXT: qc.insbi a0, -1, 16, 0
+; RV32IXQCIBMZBS-NEXT: ret
+ %or = or i32 %b, 65535
+ ret i32 %or
+}
+
define i32 @test_insbi_shifted_mask(i32 %a) nounwind {
; RV32I-LABEL: test_insbi_shifted_mask:
; RV32I: # %bb.0:
@@ -67,6 +90,36 @@ define i32 @test_insbi_shifted_mask(i32 %a) nounwind {
ret i32 %or
}
+define i32 @test_insbi_shifted_mask_multiple_uses(i32 %a) nounwind {
+; RV32I-LABEL: test_insbi_shifted_mask_multiple_uses:
+; RV32I: # %bb.0:
+; RV32I-NEXT: lui a1, 15
+; RV32I-NEXT: or a1, a0, a1
+; RV32I-NEXT: addi a0, a0, 10
+; RV32I-NEXT: xor a0, a1, a0
+; RV32I-NEXT: ret
+;
+; RV32IXQCIBM-LABEL: test_insbi_shifted_mask_multiple_uses:
+; RV32IXQCIBM: # %bb.0:
+; RV32IXQCIBM-NEXT: lui a1, 15
+; RV32IXQCIBM-NEXT: or a1, a1, a0
+; RV32IXQCIBM-NEXT: addi a0, a0, 10
+; RV32IXQCIBM-NEXT: xor a0, a0, a1
+; RV32IXQCIBM-NEXT: ret
+;
+; RV32IXQCIBMZBS-LABEL: test_insbi_shifted_mask_multiple_uses:
+; RV32IXQCIBMZBS: # %bb.0:
+; RV32IXQCIBMZBS-NEXT: lui a1, 15
+; RV32IXQCIBMZBS-NEXT: or a1, a1, a0
+; RV32IXQCIBMZBS-NEXT: addi a0, a0, 10
+; RV32IXQCIBMZBS-NEXT: xor a0, a0, a1
+; RV32IXQCIBMZBS-NEXT: ret
+ %or = or i32 %a, 61440
+ %add = add i32 %a, 10
+ %xor = xor i32 %or, %add
+ ret i32 %xor
+}
+
define i32 @test_single_bit_set(i32 %a) nounwind {
; RV32I-LABEL: test_single_bit_set:
; RV32I: # %bb.0:
From 04d4be501dc83fe411193a46c10e898898552731 Mon Sep 17 00:00:00 2001
From: Eli Friedman <efrie...@quicinc.com>
Date: Tue, 15 Jul 2025 15:39:51 -0700
Subject: [PATCH 09/22] [libclang] Fix version for symbol clang_visitCXXMethods
(#148958)
Happened to spot this while looking at libclang.map for other reasons.
clang_visitCXXMethods was added in LLVM 21, not LLVM 20.
(cherry picked from commit 116110e1a93531a64d82f049b6e36403bc14f278)
---
clang/tools/libclang/libclang.map | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/clang/tools/libclang/libclang.map
b/clang/tools/libclang/libclang.map
index d140a71e771a0..49c472e3833fd 100644
--- a/clang/tools/libclang/libclang.map
+++ b/clang/tools/libclang/libclang.map
@@ -435,12 +435,12 @@ LLVM_20 {
clang_getTypePrettyPrinted;
clang_isBeforeInTranslationUnit;
clang_visitCXXBaseClasses;
- clang_visitCXXMethods;
};
LLVM_21 {
global:
clang_getFullyQualifiedName;
+ clang_visitCXXMethods;
clang_Cursor_getGCCAssemblyTemplate;
clang_Cursor_isGCCAssemblyHasGoto;
clang_Cursor_getGCCAssemblyNumOutputs;
From adb453c8a615abbb9890fa412f964980c82f40bc Mon Sep 17 00:00:00 2001
From: Jordan Rupprecht <ruppre...@google.com>
Date: Wed, 16 Jul 2025 04:31:48 -0500
Subject: [PATCH 10/22] [Support][BLAKE3] Prefix more blake3 methods (#149007)
Added by #147948, blake3_xof_many and blake3_compress_subtree_wide cause
conflicts when linking llvm and blake3 statically into the same binary.
Similar to #148607.
(cherry picked from commit 60579ec3059b2b6cc9dad90eaac1ed363fc395a7)
---
llvm/lib/Support/BLAKE3/llvm_blake3_prefix.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/llvm/lib/Support/BLAKE3/llvm_blake3_prefix.h
b/llvm/lib/Support/BLAKE3/llvm_blake3_prefix.h
index d5be360815add..d24657465dd8f 100644
--- a/llvm/lib/Support/BLAKE3/llvm_blake3_prefix.h
+++ b/llvm/lib/Support/BLAKE3/llvm_blake3_prefix.h
@@ -10,7 +10,9 @@
#define blake3_hasher llvm_blake3_hasher
#define blake3_chunk_state llvm_blake3_chunk_state
#define blake3_compress_in_place llvm_blake3_compress_in_place
+#define blake3_compress_subtree_wide llvm_blake3_compress_subtree_wide
#define blake3_compress_xof llvm_blake3_compress_xof
+#define blake3_xof_many llvm_blake3_xof_many
#define blake3_hash_many llvm_blake3_hash_many
#define blake3_simd_degree llvm_blake3_simd_degree
#define blake3_compress_in_place_portable
llvm_blake3_compress_in_place_portable
From 6ee4eedc2a5b9c52008651ebd8aaf240adc23fcb Mon Sep 17 00:00:00 2001
From: Sirraide <aeternalm...@gmail.com>
Date: Wed, 16 Jul 2025 15:48:53 +0200
Subject: [PATCH 11/22] [Clang] Reintroduce obsolete libclang symbols to avoid
an ABI break (#149079)
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
For more context, see
https://github.com/llvm/llvm-project/pull/119269#issuecomment-3075444493,
but briefly, when removing ARCMigrate, I also removed some symbols in
libclang, which constitutes an ABI break that we don’t want, so this pr
reintroduces the removed symbols; the declarations are marked as
deprecated for future removal, and the implementations print an error
and do nothing, which is what we used to do when ARCMigrate was
disabled.
(cherry picked from commit 1600450f9098e5c9cb26840bd53f1be8a2559b7d)
---
clang/include/clang-c/Index.h | 15 ++++++
clang/tools/libclang/CMakeLists.txt | 1 +
clang/tools/libclang/Obsolete.cpp | 48 +++++++++++++++++++
.../secondary/clang/tools/libclang/BUILD.gn | 1 +
4 files changed, 65 insertions(+)
create mode 100644 clang/tools/libclang/Obsolete.cpp
diff --git a/clang/include/clang-c/Index.h b/clang/include/clang-c/Index.h
index c35311c886413..b929585205aee 100644
--- a/clang/include/clang-c/Index.h
+++ b/clang/include/clang-c/Index.h
@@ -6953,6 +6953,21 @@ clang_getCursorUnaryOperatorKind(CXCursor cursor);
* @}
*/
+CINDEX_DEPRECATED
+typedef void *CXRemapping;
+
+CINDEX_DEPRECATED CINDEX_LINKAGE CXRemapping clang_getRemappings(const char *);
+
+CINDEX_DEPRECATED CINDEX_LINKAGE CXRemapping
+clang_getRemappingsFromFileList(const char **, unsigned);
+
+CINDEX_DEPRECATED CINDEX_LINKAGE unsigned clang_remap_getNumFiles(CXRemapping);
+
+CINDEX_DEPRECATED CINDEX_LINKAGE void
+clang_remap_getFilenames(CXRemapping, unsigned, CXString *, CXString *);
+
+CINDEX_DEPRECATED CINDEX_LINKAGE void clang_remap_dispose(CXRemapping);
+
LLVM_CLANG_C_EXTERN_C_END
#endif
diff --git a/clang/tools/libclang/CMakeLists.txt
b/clang/tools/libclang/CMakeLists.txt
index b6662b66206b2..2b1e266f07392 100644
--- a/clang/tools/libclang/CMakeLists.txt
+++ b/clang/tools/libclang/CMakeLists.txt
@@ -42,6 +42,7 @@ set(SOURCES
Indexing.cpp
FatalErrorHandler.cpp
Rewrite.cpp
+ Obsolete.cpp
ADDITIONAL_HEADERS
CIndexDiagnostic.h
diff --git a/clang/tools/libclang/Obsolete.cpp
b/clang/tools/libclang/Obsolete.cpp
new file mode 100644
index 0000000000000..3596f76e1be6f
--- /dev/null
+++ b/clang/tools/libclang/Obsolete.cpp
@@ -0,0 +1,48 @@
+//===- Obsolete.cpp - Obsolete libclang functions and types -------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--------------------------------------------------------------------===//
+//
+// This file contains libclang symbols whose underlying functionality has been
+// removed from Clang, but which need to be kept around so as to retain ABI
+// compatibility.
+//
+//===--------------------------------------------------------------------===//
+
+#include "clang-c/CXString.h"
+#include "clang-c/Index.h"
+#include "clang-c/Platform.h"
+#include "llvm/Support/raw_ostream.h"
+
+extern "C" {
+
+// The functions below used to be part of the C API for ARCMigrate, which has
+// since been removed from Clang; they already used to print an error if Clang
+// was compiled without arcmt support, so we continue doing so.
+CXRemapping clang_getRemappings(const char *) {
+ llvm::errs() << "error: ARCMigrate has been removed from Clang";
+ return nullptr;
+}
+
+CXRemapping clang_getRemappingsFromFileList(const char **, unsigned) {
+ llvm::errs() << "error: ARCMigrate has been removed from Clang";
+ return nullptr;
+}
+
+unsigned clang_remap_getNumFiles(CXRemapping) {
+ llvm::errs() << "error: ARCMigrate has been removed from Clang";
+ return 0;
+}
+
+void clang_remap_getFilenames(CXRemapping, unsigned, CXString *, CXString *) {
+ llvm::errs() << "error: ARCMigrate has been removed from Clang";
+}
+
+void clang_remap_dispose(CXRemapping) {
+ llvm::errs() << "error: ARCMigrate has been removed from Clang";
+}
+
+} // extern "C"
diff --git a/llvm/utils/gn/secondary/clang/tools/libclang/BUILD.gn
b/llvm/utils/gn/secondary/clang/tools/libclang/BUILD.gn
index 8f7beea152ab7..30b8bb61184bd 100644
--- a/llvm/utils/gn/secondary/clang/tools/libclang/BUILD.gn
+++ b/llvm/utils/gn/secondary/clang/tools/libclang/BUILD.gn
@@ -87,6 +87,7 @@ shared_library("libclang") {
"Index_Internal.h",
"Indexing.cpp",
"Rewrite.cpp",
+ "Obsolete.cpp",
]
if (host_os == "mac") {
ldflags = [
From 46c566f579f2ebe8abe8871c3527979dbc558e70 Mon Sep 17 00:00:00 2001
From: Aiden Grossman <aidengross...@google.com>
Date: Tue, 15 Jul 2025 08:10:47 -0700
Subject: [PATCH 12/22] [CI][Github] Switch windows to server 2022 (#148743)
This patch switches the windows testing over to server 2022 by switching
to the recently introduced runner set.
(cherry picked from commit 3248a6d76abccbbe78e853c76bc022b70d594347)
---
.github/workflows/premerge.yaml | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/.github/workflows/premerge.yaml b/.github/workflows/premerge.yaml
index f7a48304b82b0..ff63355222065 100644
--- a/.github/workflows/premerge.yaml
+++ b/.github/workflows/premerge.yaml
@@ -76,7 +76,7 @@ jobs:
if: >-
github.repository_owner == 'llvm' &&
(github.event_name != 'pull_request' || github.event.action !=
'closed')
- runs-on: llvm-premerge-windows-runners
+ runs-on: llvm-premerge-windows-2022-runners
defaults:
run:
shell: bash
From 7c2c20dd9c3e90772b06973fdc235971c31f3955 Mon Sep 17 00:00:00 2001
From: Matt Arsenault <matthew.arsena...@amd.com>
Date: Thu, 17 Jul 2025 08:29:09 +0900
Subject: [PATCH 13/22] RuntimeLibcalls: Fix calling conv of win32 div libcalls
(#149098)
There's probably an existing test this should be added to,
but our test coverage is really bad that this wasn't caught
by one.
(cherry picked from commit 0110168f6aa5c8a8d02ffd9e62c7929ce6d24d26)
---
llvm/include/llvm/IR/RuntimeLibcalls.td | 2 +-
.../CodeGen/X86/win32-int-runtime-libcalls.ll | 113 ++++++++++++++++++
2 files changed, 114 insertions(+), 1 deletion(-)
create mode 100644 llvm/test/CodeGen/X86/win32-int-runtime-libcalls.ll
diff --git a/llvm/include/llvm/IR/RuntimeLibcalls.td
b/llvm/include/llvm/IR/RuntimeLibcalls.td
index a6254eafa4906..9b081e9d65449 100644
--- a/llvm/include/llvm/IR/RuntimeLibcalls.td
+++ b/llvm/include/llvm/IR/RuntimeLibcalls.td
@@ -2120,7 +2120,7 @@ defvar X86CommonLibcalls =
);
defvar Windows32DivRemMulCalls =
- LibcallImpls<(add WindowsDivRemMulLibcalls),
+ LibcallsWithCC<(add WindowsDivRemMulLibcalls), X86_STDCALL,
RuntimeLibcallPredicate<"TT.isWindowsMSVCEnvironment() ||
TT.isWindowsItaniumEnvironment()">>;
def X86_32SystemLibrary
diff --git a/llvm/test/CodeGen/X86/win32-int-runtime-libcalls.ll
b/llvm/test/CodeGen/X86/win32-int-runtime-libcalls.ll
new file mode 100644
index 0000000000000..5ac90a0af2e57
--- /dev/null
+++ b/llvm/test/CodeGen/X86/win32-int-runtime-libcalls.ll
@@ -0,0 +1,113 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
UTC_ARGS: --version 5
+; RUN: llc -mtriple=i686-windows-msvc < %s | FileCheck -check-prefix=CHECK32 %s
+; RUN: llc -mtriple=x86_64-windows-msvc < %s | FileCheck -check-prefix=CHECK64
%s
+
+define i64 @test_sdiv_i64(i64 %a, i64 %b) {
+; CHECK32-LABEL: test_sdiv_i64:
+; CHECK32: # %bb.0:
+; CHECK32-NEXT: pushl {{[0-9]+}}(%esp)
+; CHECK32-NEXT: pushl {{[0-9]+}}(%esp)
+; CHECK32-NEXT: pushl {{[0-9]+}}(%esp)
+; CHECK32-NEXT: pushl {{[0-9]+}}(%esp)
+; CHECK32-NEXT: calll __alldiv
+; CHECK32-NEXT: retl
+;
+; CHECK64-LABEL: test_sdiv_i64:
+; CHECK64: # %bb.0:
+; CHECK64-NEXT: movq %rdx, %r8
+; CHECK64-NEXT: movq %rcx, %rax
+; CHECK64-NEXT: cqto
+; CHECK64-NEXT: idivq %r8
+; CHECK64-NEXT: retq
+ %ret = sdiv i64 %a, %b
+ ret i64 %ret
+}
+
+define i64 @test_srem_i64(i64 %a, i64 %b) {
+; CHECK32-LABEL: test_srem_i64:
+; CHECK32: # %bb.0:
+; CHECK32-NEXT: pushl {{[0-9]+}}(%esp)
+; CHECK32-NEXT: pushl {{[0-9]+}}(%esp)
+; CHECK32-NEXT: pushl {{[0-9]+}}(%esp)
+; CHECK32-NEXT: pushl {{[0-9]+}}(%esp)
+; CHECK32-NEXT: calll __allrem
+; CHECK32-NEXT: retl
+;
+; CHECK64-LABEL: test_srem_i64:
+; CHECK64: # %bb.0:
+; CHECK64-NEXT: movq %rdx, %r8
+; CHECK64-NEXT: movq %rcx, %rax
+; CHECK64-NEXT: cqto
+; CHECK64-NEXT: idivq %r8
+; CHECK64-NEXT: movq %rdx, %rax
+; CHECK64-NEXT: retq
+ %ret = srem i64 %a, %b
+ ret i64 %ret
+}
+
+define i64 @test_udiv_i64(i64 %a, i64 %b) {
+; CHECK32-LABEL: test_udiv_i64:
+; CHECK32: # %bb.0:
+; CHECK32-NEXT: pushl {{[0-9]+}}(%esp)
+; CHECK32-NEXT: pushl {{[0-9]+}}(%esp)
+; CHECK32-NEXT: pushl {{[0-9]+}}(%esp)
+; CHECK32-NEXT: pushl {{[0-9]+}}(%esp)
+; CHECK32-NEXT: calll __aulldiv
+; CHECK32-NEXT: retl
+;
+; CHECK64-LABEL: test_udiv_i64:
+; CHECK64: # %bb.0:
+; CHECK64-NEXT: movq %rdx, %r8
+; CHECK64-NEXT: movq %rcx, %rax
+; CHECK64-NEXT: xorl %edx, %edx
+; CHECK64-NEXT: divq %r8
+; CHECK64-NEXT: retq
+ %ret = udiv i64 %a, %b
+ ret i64 %ret
+}
+
+define i64 @test_urem_i64(i64 %a, i64 %b) {
+; CHECK32-LABEL: test_urem_i64:
+; CHECK32: # %bb.0:
+; CHECK32-NEXT: pushl {{[0-9]+}}(%esp)
+; CHECK32-NEXT: pushl {{[0-9]+}}(%esp)
+; CHECK32-NEXT: pushl {{[0-9]+}}(%esp)
+; CHECK32-NEXT: pushl {{[0-9]+}}(%esp)
+; CHECK32-NEXT: calll __aullrem
+; CHECK32-NEXT: retl
+;
+; CHECK64-LABEL: test_urem_i64:
+; CHECK64: # %bb.0:
+; CHECK64-NEXT: movq %rdx, %r8
+; CHECK64-NEXT: movq %rcx, %rax
+; CHECK64-NEXT: xorl %edx, %edx
+; CHECK64-NEXT: divq %r8
+; CHECK64-NEXT: movq %rdx, %rax
+; CHECK64-NEXT: retq
+ %ret = urem i64 %a, %b
+ ret i64 %ret
+}
+
+define i64 @test_mul_i64(i64 %a, i64 %b) {
+; CHECK32-LABEL: test_mul_i64:
+; CHECK32: # %bb.0:
+; CHECK32-NEXT: pushl %esi
+; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %esi
+; CHECK32-NEXT: movl %ecx, %eax
+; CHECK32-NEXT: mull %esi
+; CHECK32-NEXT: imull {{[0-9]+}}(%esp), %ecx
+; CHECK32-NEXT: addl %ecx, %edx
+; CHECK32-NEXT: imull {{[0-9]+}}(%esp), %esi
+; CHECK32-NEXT: addl %esi, %edx
+; CHECK32-NEXT: popl %esi
+; CHECK32-NEXT: retl
+;
+; CHECK64-LABEL: test_mul_i64:
+; CHECK64: # %bb.0:
+; CHECK64-NEXT: movq %rcx, %rax
+; CHECK64-NEXT: imulq %rdx, %rax
+; CHECK64-NEXT: retq
+ %ret = mul i64 %a, %b
+ ret i64 %ret
+}
From 194dd6679f8369ee343ba3eaf945f49b4e6f6211 Mon Sep 17 00:00:00 2001
From: Nikita Popov <npo...@redhat.com>
Date: Wed, 16 Jul 2025 17:49:19 +0200
Subject: [PATCH 14/22] [Support][BLAKE3] Restore static on blake3_hash4_neon
(#149046)
This was dropped in #147948 and causes symbol conflicts if libblake3 is
also linked.
(cherry picked from commit 1754a7d5733d5305e4ec25ef0945b39d6882bb28)
---
llvm/lib/Support/BLAKE3/blake3_neon.c | 9 +++++----
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/llvm/lib/Support/BLAKE3/blake3_neon.c
b/llvm/lib/Support/BLAKE3/blake3_neon.c
index 9629e10836864..ee36721f87573 100644
--- a/llvm/lib/Support/BLAKE3/blake3_neon.c
+++ b/llvm/lib/Support/BLAKE3/blake3_neon.c
@@ -245,10 +245,11 @@ INLINE void load_counters4(uint64_t counter, bool
increment_counter,
counter_high(counter + (mask & 2)), counter_high(counter + (mask & 3)));
}
-void blake3_hash4_neon(const uint8_t *const *inputs, size_t blocks,
- const uint32_t key[8], uint64_t counter,
- bool increment_counter, uint8_t flags,
- uint8_t flags_start, uint8_t flags_end, uint8_t *out) {
+static void blake3_hash4_neon(const uint8_t *const *inputs, size_t blocks,
+ const uint32_t key[8], uint64_t counter,
+ bool increment_counter, uint8_t flags,
+ uint8_t flags_start, uint8_t flags_end,
+ uint8_t *out) {
uint32x4_t h_vecs[8] = {
set1_128(key[0]), set1_128(key[1]), set1_128(key[2]), set1_128(key[3]),
set1_128(key[4]), set1_128(key[5]), set1_128(key[6]), set1_128(key[7]),
From 68e17aec8f9fe1dea2ee10066a55e79eeab571a0 Mon Sep 17 00:00:00 2001
From: Jonas Devlieghere <jo...@devlieghere.com>
Date: Wed, 16 Jul 2025 10:05:05 -0700
Subject: [PATCH 15/22] [lldb] Add a release note for MCP support
---
llvm/docs/ReleaseNotes.md | 2 ++
1 file changed, 2 insertions(+)
diff --git a/llvm/docs/ReleaseNotes.md b/llvm/docs/ReleaseNotes.md
index 6191a915051fa..0d63608389520 100644
--- a/llvm/docs/ReleaseNotes.md
+++ b/llvm/docs/ReleaseNotes.md
@@ -315,6 +315,8 @@ Changes to LLDB
nothing at all
* Changed the format of opcode bytes to match llvm-objdump when disassembling
RISC-V code with `disassemble`'s `--byte` option.
+* LLDB added native support for the Model Context Protocol (MCP). An MCP
+ server can be started with the `protocol-server start MCP` command.
### Changes to lldb-dap
From 38158a93d8d9598fb3b827b8513f67771b8fcbfd Mon Sep 17 00:00:00 2001
From: Jonas Devlieghere <jo...@devlieghere.com>
Date: Wed, 16 Jul 2025 09:31:43 -0700
Subject: [PATCH 16/22] [lldb] Document MCP tools & resources (#148708)
Add documentation for the tools and resources exposed by LLDB's MCP
server.
(cherry picked from commit e8dc96d9de14c4b2317b11b8bc6e9310113697b3)
---
lldb/docs/use/mcp.md | 64 +++++++++++++++++++++++++++++++++++++++++++-
1 file changed, 63 insertions(+), 1 deletion(-)
diff --git a/lldb/docs/use/mcp.md b/lldb/docs/use/mcp.md
index 375c164fe771c..b7474246b54f3 100644
--- a/lldb/docs/use/mcp.md
+++ b/lldb/docs/use/mcp.md
@@ -75,7 +75,69 @@ Configuration example for [Visual Studio
Code](https://code.visualstudio.com/doc
}
```
-### Troubleshooting
+## Tools
+
+Tools are a primitive in the Model Context Protocol that enable servers to
+expose functionality to clients.
+
+LLDB's MCP integration exposes one tool, named `lldb_command` which allows the
+model to run the same commands a user would type in the LLDB command
+interpreter. It takes two arguments:
+
+1. The unique debugger ID as a number.
+2. The command and its arguments as a string.
+
+## Resources
+
+Resources are a primitive in the Model Context Protocol that allow servers to
+expose content that can be read by clients.
+
+LLDB's MCP integration exposes a resource for each debugger and target
+instance. Debugger resources are accessible using the following URI:
+
+```
+lldb://debugger/<debugger id>
+```
+
+Example output:
+
+```json
+{
+ "contents": [
+ {
+ "uri": "lldb://debugger/1",
+ "mimeType": "application/json",
+ "text": "{\"debugger_id\":1,\"name\":\"debugger_1\",\"num_targets\":1}"
+ }
+ ]
+}
+```
+
+Debuggers can contain one or more targets, which are accessible using the
+following URI:
+
+```
+lldb://debugger/<debugger id>/target/<target idx>
+```
+
+Example output:
+
+```json
+{
+ "contents": [
+ {
+ "uri": "lldb://debugger/1/target/0",
+ "mimeType": "application/json",
+ "text":
"{\"arch\":\"arm64-apple-macosx26.0.0\",\"debugger_id\":1,\"dummy\":false,\"path\":\"/bin/count\",\"platform\":\"host\",\"selected\":true,\"target_idx\":0}"
+ }
+ ]
+}
+```
+
+Note that unlike the debugger id, which is unique, the target index is not
+stable and may be reused when a target is removed and a new target is added.
+
+## Troubleshooting
The MCP server uses the `Host` log channel. You can enable logging with the
`log enable` command.
From 2067574f54dd076fec4a5397bb2de7ad813e7e93 Mon Sep 17 00:00:00 2001
From: Eli Friedman <efrie...@quicinc.com>
Date: Tue, 15 Jul 2025 10:01:27 -0700
Subject: [PATCH 17/22] [clang] Fix pointer comparisons between pointers to
constexpr-unknown (#147663)
A constexpr-unknown reference can be equal to an arbitrary value, except
values allocated during constant evaluation. Fix the handling.
The standard is unclear exactly which pointer comparisons count as
"unknown" in this context; for example, in some cases we could use
alignment to prove two constexpr-unknown references are not equal. I
decided to ignore all the cases involving variables not allocated during
constant evaluation.
While looking at this, I also spotted that there might be issues with
lifetimes, but I didn't try to address it.
(cherry picked from commit 20c8e3c2a4744524396cc473a370cfb7855850b6)
---
clang/docs/ReleaseNotes.rst | 1 +
clang/lib/AST/ExprConstant.cpp | 10 +++---
.../SemaCXX/constant-expression-cxx14.cpp | 15 +++++++++
.../SemaCXX/constant-expression-p2280r4.cpp | 32 ++++++++++++++-----
4 files changed, 44 insertions(+), 14 deletions(-)
diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst
index bd7a4b20242fd..2add72a1654b1 100644
--- a/clang/docs/ReleaseNotes.rst
+++ b/clang/docs/ReleaseNotes.rst
@@ -967,6 +967,7 @@ Bug Fixes to C++ Support
- Fix a crash with NTTP when instantiating local class.
- Fixed a crash involving list-initialization of an empty class with a
non-empty initializer list. (#GH147949)
+- Fixed constant evaluation of equality comparisons of constexpr-unknown
references. (#GH147663)
Bug Fixes to AST Handling
^^^^^^^^^^^^^^^^^^^^^^^^^
diff --git a/clang/lib/AST/ExprConstant.cpp b/clang/lib/AST/ExprConstant.cpp
index 419dd5dbdc695..1b33b6706e204 100644
--- a/clang/lib/AST/ExprConstant.cpp
+++ b/clang/lib/AST/ExprConstant.cpp
@@ -14478,12 +14478,6 @@ EvaluateComparisonBinaryOperator(EvalInfo &Info, const
BinaryOperator *E,
if (!EvaluatePointer(E->getRHS(), RHSValue, Info) || !LHSOK)
return false;
- // If we have Unknown pointers we should fail if they are not global
values.
- if (!(IsGlobalLValue(LHSValue.getLValueBase()) &&
- IsGlobalLValue(RHSValue.getLValueBase())) &&
- (LHSValue.AllowConstexprUnknown || RHSValue.AllowConstexprUnknown))
- return false;
-
// Reject differing bases from the normal codepath; we special-case
// comparisons to null.
if (!HasSameBase(LHSValue, RHSValue)) {
@@ -14545,6 +14539,10 @@ EvaluateComparisonBinaryOperator(EvalInfo &Info, const
BinaryOperator *E,
(LHSValue.Base && isZeroSized(RHSValue)))
return DiagComparison(
diag::note_constexpr_pointer_comparison_zero_sized);
+ if (LHSValue.AllowConstexprUnknown || RHSValue.AllowConstexprUnknown)
+ return DiagComparison(
+ diag::note_constexpr_pointer_comparison_unspecified);
+ // FIXME: Verify both variables are live.
return Success(CmpResult::Unequal, E);
}
diff --git a/clang/test/SemaCXX/constant-expression-cxx14.cpp
b/clang/test/SemaCXX/constant-expression-cxx14.cpp
index e16a69df3830d..e93b98c185a82 100644
--- a/clang/test/SemaCXX/constant-expression-cxx14.cpp
+++ b/clang/test/SemaCXX/constant-expression-cxx14.cpp
@@ -1321,3 +1321,18 @@ constexpr bool check = different_in_loop();
// expected-error@-1 {{}} expected-note@-1 {{in call}}
}
+
+namespace comparison_dead_variable {
+ constexpr bool f() {
+ int *p1 = 0, *p2 = 0;
+ {
+ int x = 0; p1 = &x;
+ }
+ {
+ int x = 0; p2 = &x;
+ }
+ return p1 != p2;
+ }
+ // FIXME: This should fail.
+ static_assert(f(),"");
+}
diff --git a/clang/test/SemaCXX/constant-expression-p2280r4.cpp
b/clang/test/SemaCXX/constant-expression-p2280r4.cpp
index dffb386f530f4..03fea91169787 100644
--- a/clang/test/SemaCXX/constant-expression-p2280r4.cpp
+++ b/clang/test/SemaCXX/constant-expression-p2280r4.cpp
@@ -319,7 +319,7 @@ namespace casting {
}
namespace pointer_comparisons {
- extern int &extern_n; // interpreter-note 2 {{declared here}}
+ extern int &extern_n; // interpreter-note 4 {{declared here}}
extern int &extern_n2;
constexpr int f1(bool b, int& n) {
if (b) {
@@ -330,14 +330,30 @@ namespace pointer_comparisons {
// FIXME: interpreter incorrectly rejects; both sides are the same
constexpr-unknown value.
static_assert(f1(false, extern_n)); // interpreter-error {{static assertion
expression is not an integral constant expression}} \
// interpreter-note {{initializer of
'extern_n' is unknown}}
- // FIXME: We should diagnose this: we don't know if the references bind
- // to the same object.
- static_assert(&extern_n != &extern_n2); // interpreter-error {{static
assertion expression is not an integral constant expression}} \
+ static_assert(&extern_n != &extern_n2); // expected-error {{static assertion
expression is not an integral constant expression}} \
+ // nointerpreter-note {{comparison
between pointers to unrelated objects '&extern_n' and '&extern_n2' has
unspecified value}} \
// interpreter-note {{initializer of
'extern_n' is unknown}}
void f2(const int &n) {
- // FIXME: We should not diagnose this: the two objects provably have
- // different addresses because the lifetime of "n" extends across
- // the initialization.
- constexpr int x = &x == &n; // nointerpreter-error {{must be initialized
by a constant expression}}
+ constexpr int x = &x == &n; // nointerpreter-error {{must be initialized
by a constant expression}} \
+ // nointerpreter-note {{comparison between
pointers to unrelated objects '&x' and '&n' has unspecified value}}
+ // Distinct variables are not equal, even if they're local variables.
+ constexpr int y = &x == &y;
+ static_assert(!y);
}
+ constexpr int f3() {
+ int x;
+ return &x == &extern_n; // nointerpreter-note {{comparison between
pointers to unrelated objects '&x' and '&extern_n' has unspecified value}} \
+ // interpreter-note {{initializer of 'extern_n' is
unknown}}
+ }
+ static_assert(!f3()); // expected-error {{static assertion expression is not
an integral constant expression}} \
+ // expected-note {{in call to 'f3()'}}
+ constexpr int f4() {
+ int *p = new int;
+ bool b = p == &extern_n; // nointerpreter-note {{comparison between
pointers to unrelated objects '&{*new int#0}' and '&extern_n' has unspecified
value}} \
+ // interpreter-note {{initializer of 'extern_n'
is unknown}}
+ delete p;
+ return b;
+ }
+ static_assert(!f4()); // expected-error {{static assertion expression is not
an integral constant expression}} \
+ // expected-note {{in call to 'f4()'}}
}
From ad9051049d4360a8409eb4c552ba92524a41c13b Mon Sep 17 00:00:00 2001
From: Yuxuan Chen <y...@fb.com>
Date: Tue, 15 Jul 2025 15:02:32 -0700
Subject: [PATCH 18/22] [Clang] Fix FE crash during CGCoroutine GRO Alloca
Emission (#148962)
Fixes: https://github.com/llvm/llvm-project/issues/148953
Currently when coroutine return object type is const qualified, we don't
do direct emission. The regular emission logic assumed that the auto var
emission will always result in an `AllocaInst`. However, based on my
findings, NRVO var emissions don't result in `AllocaInst`s. Therefore,
this
[assertion](https://github.com/llvm/llvm-project/blob/1a940bfff9176fb38a71b0045d7ae25df9a4ca7d/clang/lib/CodeGen/CGCoroutine.cpp#L712)
will fail.
Since the NRVOed returned object don't live on the coroutine frame, we
won't have the problem of it outliving the coroutine frame, therefore,
we can safely omit this metadata.
(cherry picked from commit c36156de45a0f5e24e7a4ee2259c3302ea814785)
---
clang/lib/CodeGen/CGCoroutine.cpp | 14 +++++++----
clang/test/CodeGenCoroutines/coro-gro.cpp | 29 ++++++++++++++++++++++-
2 files changed, 37 insertions(+), 6 deletions(-)
diff --git a/clang/lib/CodeGen/CGCoroutine.cpp
b/clang/lib/CodeGen/CGCoroutine.cpp
index 0fc488e98aaf0..117ef3d16e21b 100644
--- a/clang/lib/CodeGen/CGCoroutine.cpp
+++ b/clang/lib/CodeGen/CGCoroutine.cpp
@@ -707,11 +707,15 @@ struct GetReturnObjectManager {
Builder.CreateStore(Builder.getFalse(), GroActiveFlag);
GroEmission = CGF.EmitAutoVarAlloca(*GroVarDecl);
- auto *GroAlloca = dyn_cast_or_null<llvm::AllocaInst>(
- GroEmission.getOriginalAllocatedAddress().getPointer());
- assert(GroAlloca && "expected alloca to be emitted");
- GroAlloca->setMetadata(llvm::LLVMContext::MD_coro_outside_frame,
- llvm::MDNode::get(CGF.CGM.getLLVMContext(), {}));
+
+ if (!GroVarDecl->isNRVOVariable()) {
+ // NRVO variables don't have allocas and won't have the same issue.
+ auto *GroAlloca = dyn_cast_or_null<llvm::AllocaInst>(
+ GroEmission.getOriginalAllocatedAddress().getPointer());
+ assert(GroAlloca && "expected alloca to be emitted");
+ GroAlloca->setMetadata(llvm::LLVMContext::MD_coro_outside_frame,
+ llvm::MDNode::get(CGF.CGM.getLLVMContext(), {}));
+ }
// Remember the top of EHStack before emitting the cleanup.
auto old_top = CGF.EHStack.stable_begin();
diff --git a/clang/test/CodeGenCoroutines/coro-gro.cpp
b/clang/test/CodeGenCoroutines/coro-gro.cpp
index b62134317cef2..037fd03349e76 100644
--- a/clang/test/CodeGenCoroutines/coro-gro.cpp
+++ b/clang/test/CodeGenCoroutines/coro-gro.cpp
@@ -106,4 +106,31 @@ invoker g() {
// CHECK: call void
@_ZN7invoker15invoker_promise17get_return_objectEv({{.*}} %[[AggRes]]
co_return;
}
-// CHECK: ![[OutFrameMetadata]] = !{}
\ No newline at end of file
+
+namespace gh148953 {
+
+struct Task {
+ struct promise_type {
+ Task get_return_object();
+ std::suspend_always initial_suspend() { return {}; }
+ std::suspend_always final_suspend() noexcept { return {}; }
+ void return_void() {}
+ void unhandled_exception() {}
+ };
+ Task() {}
+ // Different from `invoker`, this Task is copy constructible.
+ Task(const Task&) {};
+};
+
+// NRVO on const qualified return type should work.
+// CHECK: define{{.*}} void @_ZN8gh1489537exampleEv({{.*}}
sret(%"struct.gh148953::Task") align 1 %[[NrvoRes:.+]])
+const Task example() {
+ // CHECK: %[[ResultPtr:.+]] = alloca ptr
+ // CHECK: store ptr %[[NrvoRes]], ptr %[[ResultPtr]]
+ // CHECK: coro.init:
+ // CHECK: call void
@_ZN8gh1489534Task12promise_type17get_return_objectEv({{.*}} %[[NrvoRes:.+]],
{{.*}})
+ co_return;
+}
+
+} // namespace gh148953
+// CHECK: ![[OutFrameMetadata]] = !{}
From dd7710b7fda80f718f84ec7bb3ef69ec28e92614 Mon Sep 17 00:00:00 2001
From: Sirraide <aeternalm...@gmail.com>
Date: Thu, 17 Jul 2025 01:30:50 +0200
Subject: [PATCH 19/22] [Clang] Reintroduce obsolete symbols in libclang.map
(#149190)
This is a follow-up to #149079. Seems like we forgot about the fact that
the symbols also need to be in `libclang.map`.
(cherry picked from commit 7e0fde0c2f6b0b9d727ce9196956b36e91961ac4)
---
clang/tools/libclang/libclang.map | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/clang/tools/libclang/libclang.map
b/clang/tools/libclang/libclang.map
index 49c472e3833fd..3d9d2e268a611 100644
--- a/clang/tools/libclang/libclang.map
+++ b/clang/tools/libclang/libclang.map
@@ -327,6 +327,8 @@ LLVM_13 {
clang_getRange;
clang_getRangeEnd;
clang_getRangeStart;
+ clang_getRemappings;
+ clang_getRemappingsFromFileList;
clang_getResultType;
clang_getSkippedRanges;
clang_getSpecializedCursorTemplate;
@@ -387,6 +389,9 @@ LLVM_13 {
clang_parseTranslationUnit;
clang_parseTranslationUnit2;
clang_parseTranslationUnit2FullArgv;
+ clang_remap_dispose;
+ clang_remap_getFilenames;
+ clang_remap_getNumFiles;
clang_reparseTranslationUnit;
clang_saveTranslationUnit;
clang_sortCodeCompletionResults;
From 7ac3c6228233980e154cdbc294def0cc66063bc1 Mon Sep 17 00:00:00 2001
From: Corentin Jabot <corentinja...@gmail.com>
Date: Thu, 17 Jul 2025 12:32:49 +0300
Subject: [PATCH 20/22] Revert "[Clang] Do not treat Foo -> const Foo
conversion sequences as perfect" (#149272)
Reverts llvm/llvm-project#148613
Considering object argument conversion qualifications perfect leads to
situations where we prefer a non-template const qualified function over
a non-qualified template function, which is very wrong indeed.
I explored solutions to work around that, but instead, we might want to
go the GCC road and prefer the friend overload in the #147374 example,
as this seems a lot more consistent and reliable
(cherry picked from commit 28e1e7e1b4b059a2e42f68061475cddb4ad0a6a3)
---
clang/include/clang/Sema/Overload.h | 11 ++------
clang/lib/Sema/SemaOverload.cpp | 14 +---------
...overload-resolution-deferred-templates.cpp | 28 -------------------
3 files changed, 4 insertions(+), 49 deletions(-)
diff --git a/clang/include/clang/Sema/Overload.h
b/clang/include/clang/Sema/Overload.h
index 9135ff949eeab..a70335bef9dd4 100644
--- a/clang/include/clang/Sema/Overload.h
+++ b/clang/include/clang/Sema/Overload.h
@@ -350,11 +350,6 @@ class Sema;
LLVM_PREFERRED_TYPE(bool)
unsigned BindsToRvalue : 1;
- /// Whether this was an identity conversion with qualification
- /// conversion for the implicit object argument.
- LLVM_PREFERRED_TYPE(bool)
- unsigned IsImplicitObjectArgumentQualificationConversion : 1;
-
/// Whether this binds an implicit object argument to a
/// non-static member function without a ref-qualifier.
LLVM_PREFERRED_TYPE(bool)
@@ -453,11 +448,11 @@ class Sema;
#endif
return true;
}
+ if (!C.hasSameType(getFromType(), getToType(2)))
+ return false;
if (BindsToRvalue && IsLvalueReference)
return false;
- if (IsImplicitObjectArgumentQualificationConversion)
- return C.hasSameUnqualifiedType(getFromType(), getToType(2));
- return C.hasSameType(getFromType(), getToType(2));
+ return true;
}
ImplicitConversionRank getRank() const;
diff --git a/clang/lib/Sema/SemaOverload.cpp b/clang/lib/Sema/SemaOverload.cpp
index f3baf0c3ef3bc..1b54628c5e564 100644
--- a/clang/lib/Sema/SemaOverload.cpp
+++ b/clang/lib/Sema/SemaOverload.cpp
@@ -245,7 +245,6 @@ void StandardConversionSequence::setAsIdentityConversion() {
IsLvalueReference = true;
BindsToFunctionLvalue = false;
BindsToRvalue = false;
- IsImplicitObjectArgumentQualificationConversion = false;
BindsImplicitObjectArgumentWithoutRefQualifier = false;
ObjCLifetimeConversionBinding = false;
FromBracedInitList = false;
@@ -5318,7 +5317,6 @@ TryReferenceInit(Sema &S, Expr *Init, QualType DeclType,
ICS.Standard.DirectBinding = BindsDirectly;
ICS.Standard.IsLvalueReference = !isRValRef;
ICS.Standard.BindsToFunctionLvalue = T2->isFunctionType();
- ICS.Standard.IsImplicitObjectArgumentQualificationConversion = false;
ICS.Standard.BindsToRvalue = InitCategory.isRValue();
ICS.Standard.BindsImplicitObjectArgumentWithoutRefQualifier = false;
ICS.Standard.ObjCLifetimeConversionBinding =
@@ -5498,7 +5496,6 @@ TryReferenceInit(Sema &S, Expr *Init, QualType DeclType,
ICS.Standard.IsLvalueReference = !isRValRef;
ICS.Standard.BindsToFunctionLvalue = false;
ICS.Standard.BindsToRvalue = true;
- ICS.Standard.IsImplicitObjectArgumentQualificationConversion = false;
ICS.Standard.BindsImplicitObjectArgumentWithoutRefQualifier = false;
ICS.Standard.ObjCLifetimeConversionBinding = false;
} else if (ICS.isUserDefined()) {
@@ -5521,8 +5518,6 @@ TryReferenceInit(Sema &S, Expr *Init, QualType DeclType,
ICS.UserDefined.After.IsLvalueReference = !isRValRef;
ICS.UserDefined.After.BindsToFunctionLvalue = false;
ICS.UserDefined.After.BindsToRvalue = !LValRefType;
- ICS.UserDefined.After.IsImplicitObjectArgumentQualificationConversion =
- false;
ICS.UserDefined.After.BindsImplicitObjectArgumentWithoutRefQualifier =
false;
ICS.UserDefined.After.ObjCLifetimeConversionBinding = false;
ICS.UserDefined.After.FromBracedInitList = false;
@@ -5807,7 +5802,6 @@ TryListConversion(Sema &S, InitListExpr *From, QualType
ToType,
StandardConversionSequence &SCS = Result.isStandard() ? Result.Standard :
Result.UserDefined.After;
SCS.ReferenceBinding = true;
- SCS.IsImplicitObjectArgumentQualificationConversion = false;
SCS.IsLvalueReference = ToType->isLValueReferenceType();
SCS.BindsToRvalue = true;
SCS.BindsToFunctionLvalue = false;
@@ -6005,12 +5999,8 @@ static ImplicitConversionSequence
TryObjectArgumentInitialization(
// affects the conversion rank.
QualType ClassTypeCanon = S.Context.getCanonicalType(ClassType);
ImplicitConversionKind SecondKind;
- bool IsQualificationConversion = false;
- if (ImplicitParamType.getCanonicalType() == FromTypeCanon) {
+ if (ClassTypeCanon == FromTypeCanon.getLocalUnqualifiedType()) {
SecondKind = ICK_Identity;
- } else if (ClassTypeCanon == FromTypeCanon.getLocalUnqualifiedType()) {
- SecondKind = ICK_Identity;
- IsQualificationConversion = true;
} else if (S.IsDerivedFrom(Loc, FromType, ClassType)) {
SecondKind = ICK_Derived_To_Base;
} else if (!Method->isExplicitObjectMemberFunction()) {
@@ -6051,8 +6041,6 @@ static ImplicitConversionSequence
TryObjectArgumentInitialization(
ICS.Standard.setFromType(FromType);
ICS.Standard.setAllToTypes(ImplicitParamType);
ICS.Standard.ReferenceBinding = true;
- ICS.Standard.IsImplicitObjectArgumentQualificationConversion =
- IsQualificationConversion;
ICS.Standard.DirectBinding = true;
ICS.Standard.IsLvalueReference = Method->getRefQualifier() != RQ_RValue;
ICS.Standard.BindsToFunctionLvalue = false;
diff --git a/clang/test/SemaCXX/overload-resolution-deferred-templates.cpp
b/clang/test/SemaCXX/overload-resolution-deferred-templates.cpp
index 135865c8450f5..46c3670848529 100644
--- a/clang/test/SemaCXX/overload-resolution-deferred-templates.cpp
+++ b/clang/test/SemaCXX/overload-resolution-deferred-templates.cpp
@@ -283,31 +283,3 @@ void f() {
}
#endif
-
-namespace GH147374 {
-
-struct String {};
-template <typename T> void operator+(T, String &&) = delete;
-
-struct Bar {
- void operator+(String) const; // expected-note {{candidate function}}
- friend void operator+(Bar, String) {}; // expected-note {{candidate
function}}
-};
-
-struct Baz {
- void operator+(String); // expected-note {{candidate function}}
- friend void operator+(Baz, String) {}; // expected-note {{candidate
function}}
-};
-
-void test() {
- Bar a;
- String b;
- a + b;
- //expected-error@-1 {{use of overloaded operator '+' is ambiguous (with
operand types 'Bar' and 'String')}}
-
- Baz z;
- z + b;
- //expected-error@-1 {{use of overloaded operator '+' is ambiguous (with
operand types 'Baz' and 'String')}}
-}
-
-}
From cbcb48a88c3a6227cfc09f91880d5cb92a26f5f9 Mon Sep 17 00:00:00 2001
From: Tobias Hieta <tob...@hieta.se>
Date: Thu, 17 Jul 2025 21:02:34 +0200
Subject: [PATCH 21/22] Bump version to 21.1.0-rc1
---
cmake/Modules/LLVMVersion.cmake | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/cmake/Modules/LLVMVersion.cmake b/cmake/Modules/LLVMVersion.cmake
index c12240f98e97f..ef1251548ceb1 100644
--- a/cmake/Modules/LLVMVersion.cmake
+++ b/cmake/Modules/LLVMVersion.cmake
@@ -10,6 +10,6 @@ if(NOT DEFINED LLVM_VERSION_PATCH)
set(LLVM_VERSION_PATCH 0)
endif()
if(NOT DEFINED LLVM_VERSION_SUFFIX)
- set(LLVM_VERSION_SUFFIX git)
+ set(LLVM_VERSION_SUFFIX -rc1)
endif()
From c3e705d0266b9acc68341d381b33818e43b948b5 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Herv=C3=A9=20Poussineau?= <hpous...@reactos.org>
Date: Sat, 5 Jul 2025 08:58:10 +0200
Subject: [PATCH 22/22] [docs] Add clang/llvm release notes for
mipsel-windows-* targets
---
clang/docs/ReleaseNotes.rst | 2 ++
llvm/docs/ReleaseNotes.md | 2 ++
2 files changed, 4 insertions(+)
diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst
index 2add72a1654b1..d00ded7f88897 100644
--- a/clang/docs/ReleaseNotes.rst
+++ b/clang/docs/ReleaseNotes.rst
@@ -1072,6 +1072,8 @@ Windows Support
extensions are enabled. This allows for properly processing ``intsafe.h`` in
the Windows SDK.
+- Clang now supports `mipsel-windows-gnu` and `mipsel-windows-msvc` targets.
+
LoongArch Support
^^^^^^^^^^^^^^^^^
diff --git a/llvm/docs/ReleaseNotes.md b/llvm/docs/ReleaseNotes.md
index 0d63608389520..85e55908539eb 100644
--- a/llvm/docs/ReleaseNotes.md
+++ b/llvm/docs/ReleaseNotes.md
@@ -154,6 +154,7 @@ Changes to the MIPS Backend
---------------------------
* `-mcpu=i6400` and `-mcpu=i6500` were added.
+* Added support for `mipsel-windows-gnu` and `mipsel-windows-msvc` targets.
Changes to the PowerPC Backend
------------------------------
@@ -228,6 +229,7 @@ Changes to the Windows Target
* `fp128` is now passed indirectly, meaning it uses the same calling convention
as `i128`.
+* Added support for `mipsel-windows-gnu` and `mipsel-windows-msvc` targets.
Changes to the X86 Backend
--------------------------
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