================
@@ -230,10 +242,34 @@ Load(EmulateInstructionRISCV &emulator, I inst, uint64_t
(*extend)(E)) {
auto addr = LoadStoreAddr(emulator, inst);
if (!addr)
return false;
- return transformOptional(
- emulator.ReadMem<T>(*addr),
- [&](T t) { return inst.rd.Write(emulator, extend(E(t))); })
- .value_or(false);
+
+ // Set up context for the load operation, similar to ARM64
+ EmulateInstructionRISCV::Context context;
+
+ // Get register info for base register
+ std::optional<RegisterInfo> reg_info_rs1 =
+ GPREncodingToRegisterInfo(emulator, inst.rs1.rs);
+
+ if (!reg_info_rs1)
+ return false;
+
+ // Set context type based on whether this is a stack-based load
+ if (inst.rs1.rs == RISCV_GPR_SP) // x2 is the stack pointer in RISC-V
----------------
clayborg wrote:
We probably don't need this comment now that we are using `RISCV_GPR_SP`?
https://github.com/llvm/llvm-project/pull/158161
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