https://github.com/itf created https://github.com/llvm/llvm-project/pull/160550
In RISC-V, the ADDI instruction simply performs a binary addition on the registers. The same instruction is used for both signed and unsigned additions. As we are emulating the riscv behavior we should be using uint. This fix the failure with ubsan: lldb/source/Plugins/Instruction/RISCV/EmulateInstructionRISCV.cpp:807:40: runtime error: signed integer overflow: -9223372036854775808 + -16 cannot be represented in type 'int64_t' (aka 'long') >From 93420881a71412ffb92438c3eb0974c042316ba9 Mon Sep 17 00:00:00 2001 From: Ivan Tadeu Ferreira Antunes Filho <[email protected]> Date: Wed, 24 Sep 2025 12:03:13 -0400 Subject: [PATCH] [lldb][RISCV] Use uint64_t for emulating ADDI In RISC-V, the ADDI instruction simply performs a binary addition on the registers. The same instruction is used for both signed and unsigned additions. As we are emulating the riscv behavior we should be using UINT. This fix the failure w/ ubsan: lldb/source/Plugins/Instruction/RISCV/EmulateInstructionRISCV.cpp:807:40: runtime error: signed integer overflow: -9223372036854775808 + -16 cannot be represented in type 'int64_t' (aka 'long') --- .../Plugins/Instruction/RISCV/EmulateInstructionRISCV.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/lldb/source/Plugins/Instruction/RISCV/EmulateInstructionRISCV.cpp b/lldb/source/Plugins/Instruction/RISCV/EmulateInstructionRISCV.cpp index 20661290ca4c6..5c1b7d4943b3f 100644 --- a/lldb/source/Plugins/Instruction/RISCV/EmulateInstructionRISCV.cpp +++ b/lldb/source/Plugins/Instruction/RISCV/EmulateInstructionRISCV.cpp @@ -804,7 +804,7 @@ class Executor { return transformOptional( inst.rs1.ReadI64(m_emu), [&](int64_t rs1) { - int64_t result = rs1 + int64_t(SignExt(inst.imm)); + uint64_t result = rs1 + uint64_t(SignExt(inst.imm)); // Check if this is a stack pointer adjustment. if (inst.rd.rd == RISCV_GPR_SP && inst.rs1.rs == RISCV_GPR_SP) { _______________________________________________ lldb-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
