[Lldb-commits] [lldb] [lldb][RISCV] Fix GetRegisterInfo to support RISCV-32 (PR #175262)

[via lldb-commits]

https://github.com/MkDev11 updated 
https://github.com/llvm/llvm-project/pull/175262

>From 591b85b1d93df16eef1011b921fb2d793e64e4de Mon Sep 17 00:00:00 2001
From: mkdev11 <jaysmth...@gmail.com>
Date: Sat, 10 Jan 2026 00:41:01 +0200
Subject: [PATCH 1/2] [lldb][RISCV] Fix GetRegisterInfo to support RISCV-32

GetRegisterInfo in EmulateInstructionRISCV.cpp was hardcoded to use
RegisterInfoPOSIX_riscv64, which caused LLDB to assert when working
with RISCV-32 ELF files.

This patch adds a check for the architecture and uses
RegisterInfoPOSIX_riscv32 when the target is RISCV-32.

Fixes #175092
---
 .../Instruction/RISCV/EmulateInstructionRISCV.cpp   | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/lldb/source/Plugins/Instruction/RISCV/EmulateInstructionRISCV.cpp 
b/lldb/source/Plugins/Instruction/RISCV/EmulateInstructionRISCV.cpp
index 2957cb716041d..76016e4dd7cb6 100644
--- a/lldb/source/Plugins/Instruction/RISCV/EmulateInstructionRISCV.cpp
+++ b/lldb/source/Plugins/Instruction/RISCV/EmulateInstructionRISCV.cpp
@@ -7,6 +7,7 @@
 
//===----------------------------------------------------------------------===//
 
 #include "EmulateInstructionRISCV.h"
+#include "Plugins/Process/Utility/RegisterInfoPOSIX_riscv32.h"
 #include "Plugins/Process/Utility/RegisterInfoPOSIX_riscv64.h"
 #include "Plugins/Process/Utility/lldb-riscv-register-enums.h"
 #include "RISCVCInstructions.h"
@@ -1837,6 +1838,18 @@ EmulateInstructionRISCV::GetRegisterInfo(RegisterKind 
reg_kind,
     }
   }
 
+  if (m_arch.GetCore() == ArchSpec::eCore_riscv32) {
+    RegisterInfoPOSIX_riscv32 reg_info(
+        m_arch, RegisterInfoPOSIX_riscv32::eRegsetMaskAll);
+    const RegisterInfo *array = reg_info.GetRegisterInfo();
+    uint32_t length = reg_info.GetRegisterCount();
+
+    if (reg_index >= length || reg_kind != eRegisterKindLLDB)
+      return {};
+
+    return array[reg_index];
+  }
+
   RegisterInfoPOSIX_riscv64 reg_info(m_arch,
                                      
RegisterInfoPOSIX_riscv64::eRegsetMaskAll);
   const RegisterInfo *array = reg_info.GetRegisterInfo();

>From b3a6e4392f191b9f3d17a7eb9f837d1009d20930 Mon Sep 17 00:00:00 2001
From: mkdev11 <jaysmth...@gmail.com>
Date: Sun, 11 Jan 2026 22:42:51 +0200
Subject: [PATCH 2/2] Refactor GetRegisterInfo to reduce code duplication

Address review feedback by using a lambda helper function instead of
duplicating the register info retrieval logic for both RISCV-32 and
RISCV-64.
---
 .../RISCV/EmulateInstructionRISCV.cpp         | 27 +++++++++----------
 1 file changed, 13 insertions(+), 14 deletions(-)

diff --git a/lldb/source/Plugins/Instruction/RISCV/EmulateInstructionRISCV.cpp 
b/lldb/source/Plugins/Instruction/RISCV/EmulateInstructionRISCV.cpp
index 76016e4dd7cb6..f0e21b8585bb2 100644
--- a/lldb/source/Plugins/Instruction/RISCV/EmulateInstructionRISCV.cpp
+++ b/lldb/source/Plugins/Instruction/RISCV/EmulateInstructionRISCV.cpp
@@ -1838,27 +1838,26 @@ EmulateInstructionRISCV::GetRegisterInfo(RegisterKind 
reg_kind,
     }
   }
 
-  if (m_arch.GetCore() == ArchSpec::eCore_riscv32) {
-    RegisterInfoPOSIX_riscv32 reg_info(
-        m_arch, RegisterInfoPOSIX_riscv32::eRegsetMaskAll);
+  auto get_register_info_helper =
+      [reg_index,
+       reg_kind](const auto &reg_info) -> std::optional<RegisterInfo> {
     const RegisterInfo *array = reg_info.GetRegisterInfo();
-    uint32_t length = reg_info.GetRegisterCount();
+    const uint32_t length = reg_info.GetRegisterCount();
 
     if (reg_index >= length || reg_kind != eRegisterKindLLDB)
       return {};
 
     return array[reg_index];
-  }
-
-  RegisterInfoPOSIX_riscv64 reg_info(m_arch,
-                                     
RegisterInfoPOSIX_riscv64::eRegsetMaskAll);
-  const RegisterInfo *array = reg_info.GetRegisterInfo();
-  const uint32_t length = reg_info.GetRegisterCount();
-
-  if (reg_index >= length || reg_kind != eRegisterKindLLDB)
-    return {};
+  };
 
-  return array[reg_index];
+  switch (m_arch.GetCore()) {
+  case ArchSpec::eCore_riscv32:
+    return get_register_info_helper(RegisterInfoPOSIX_riscv32(
+        m_arch, RegisterInfoPOSIX_riscv32::eRegsetMaskAll));
+  default:
+    return get_register_info_helper(RegisterInfoPOSIX_riscv64(
+        m_arch, RegisterInfoPOSIX_riscv64::eRegsetMaskAll));
+  }
 }
 
 bool EmulateInstructionRISCV::SetInstruction(const Opcode &opcode,

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