https://github.com/jthackray updated https://github.com/llvm/llvm-project/pull/182410
>From 57410e014311a9fb13fcda97123c138cabe41a6f Mon Sep 17 00:00:00 2001 From: Jonathan Thackray <[email protected]> Date: Thu, 19 Feb 2026 23:54:20 +0000 Subject: [PATCH 1/3] [AArch64][llvm] Tighten SYSP; don't disassemble invalid encodings Tighten SYSP aliases, so that invalid encodings are disassembled to `<unknown>`. This is because: ``` Cn is a 4-bit unsigned immediate, in the range 8 to 9 Cm is a 4-bit unsigned immediate, in the range 0 to 7 op1 is a 3-bit unsigned immediate, in the range 0 to 6 op2 is a 3-bit unsigned immediate, in the range 0 to 7 ``` Ensure we check this when disassembling, and also constrain tablegen for compile-time errors of invalid encodings. Also adjust the testcases in `armv9-sysp-diagnostics.s` and `llvm/test/MC/AArch64/armv9a-sysp.s` as they were invalid, and added a few invalid (outside of range) SYSP-alikes to test that `<unknown>` is printed --- .../command-disassemble-aarch64-color.s | 4 +- .../command-disassemble-aarch64-extensions.s | 4 +- .../lib/Target/AArch64/AArch64InstrFormats.td | 27 ++- llvm/lib/Target/AArch64/AArch64InstrInfo.td | 10 +- .../Disassembler/AArch64Disassembler.cpp | 25 ++ .../MCTargetDesc/AArch64InstPrinter.cpp | 8 + llvm/test/MC/AArch64/armv9-sysp-diagnostics.s | 15 +- llvm/test/MC/AArch64/armv9-sysp-invalid.s | 20 ++ llvm/test/MC/AArch64/armv9a-sysp.s | 222 +++++++++--------- 9 files changed, 208 insertions(+), 127 deletions(-) create mode 100644 llvm/test/MC/AArch64/armv9-sysp-invalid.s diff --git a/lldb/test/Shell/Commands/command-disassemble-aarch64-color.s b/lldb/test/Shell/Commands/command-disassemble-aarch64-color.s index bb97680a32970..6ddde3d974adc 100644 --- a/lldb/test/Shell/Commands/command-disassemble-aarch64-color.s +++ b/lldb/test/Shell/Commands/command-disassemble-aarch64-color.s @@ -17,7 +17,7 @@ fn: crc32b w0, w0, w0 // AEK_CRC // AEK_CRYPTO enables a combination of other features smin x0, x0, #0 // AEK_CSSC - sysp #0, c2, c0, #0, x0, x1 // AEK_D128 + sysp #0, c8, c0, #0, x0, x1 // AEK_D128 sdot v0.2s, v1.8b, v2.8b // AEK_DOTPROD fmmla z0.s, z1.s, z2.s // AEK_F32MM @@ -28,6 +28,6 @@ fn: # CHECK-NEXT: [0xc] <+12>: brb iall # CHECK-NEXT: [0x10] <+16>: crc32b [0;36mw0[0m, [0;36mw0[0m, [0;36mw0[0m # CHECK-NEXT: [0x14] <+20>: smin [0;36mx0[0m, [0;36mx0[0m, [0;31m#0x0[0m -# CHECK-NEXT: [0x18] <+24>: sysp [0;31m#0x0[0m, c2, c0, [0;31m#0x0[0m, [0;36mx0[0m, [0;36mx1[0m +# CHECK-NEXT: [0x18] <+24>: sysp [0;31m#0x0[0m, c8, c0, [0;31m#0x0[0m, [0;36mx0[0m, [0;36mx1[0m # CHECK-NEXT: [0x1c] <+28>: sdot [0;36mv0[0m.2s, [0;36mv1[0m.8b, [0;36mv2[0m.8b # CHECK-NEXT: [0x20] <+32>: fmmla [0;36mz0[0m.s, [0;36mz1[0m.s, [0;36mz2[0m.s diff --git a/lldb/test/Shell/Commands/command-disassemble-aarch64-extensions.s b/lldb/test/Shell/Commands/command-disassemble-aarch64-extensions.s index 4e281332a33bb..945654e905876 100644 --- a/lldb/test/Shell/Commands/command-disassemble-aarch64-extensions.s +++ b/lldb/test/Shell/Commands/command-disassemble-aarch64-extensions.s @@ -17,7 +17,7 @@ fn: crc32b w0, w0, w0 // AEK_CRC // AEK_CRYPTO enables a combination of other features smin x0, x0, #0 // AEK_CSSC - sysp #0, c2, c0, #0, x0, x1 // AEK_D128 + sysp #0, c8, c0, #0, x0, x1 // AEK_D128 sdot v0.2s, v1.8b, v2.8b // AEK_DOTPROD fmmla z0.s, z1.s, z2.s // AEK_F32MM fmmla z0.d, z1.d, z2.d // AEK_F64MM @@ -72,7 +72,7 @@ lbl: # CHECK-NEXT: brb iall # CHECK-NEXT: crc32b w0, w0, w0 # CHECK-NEXT: smin x0, x0, #0 -# CHECK-NEXT: sysp #0x0, c2, c0, #0x0, x0, x1 +# CHECK-NEXT: sysp #0x0, c8, c0, #0x0, x0, x1 # CHECK-NEXT: sdot v0.2s, v1.8b, v2.8b # CHECK-NEXT: fmmla z0.s, z1.s, z2.s # CHECK-NEXT: fmmla z0.d, z1.d, z2.d diff --git a/llvm/lib/Target/AArch64/AArch64InstrFormats.td b/llvm/lib/Target/AArch64/AArch64InstrFormats.td index 6ca4a1778cf8f..2f92c02bbc1f4 100644 --- a/llvm/lib/Target/AArch64/AArch64InstrFormats.td +++ b/llvm/lib/Target/AArch64/AArch64InstrFormats.td @@ -2122,6 +2122,30 @@ def sys_cr_op : Operand<i32> { let OperandType = "OPERAND_IMMEDIATE"; } +// SYSP operands are more restricted than generic system CR/imm fields. +def sysp_op1 : Operand<i64>, ImmLeaf<i64, [{ + return Imm >= 0 && Imm <= 6; +}]> { + let ParserMatchClass = Imm0_7Operand; + let OperandType = "OPERAND_IMMEDIATE"; +} + +def sysp_crn_op : Operand<i32>, ImmLeaf<i32, [{ + return Imm == 8 || Imm == 9; +}]> { + let PrintMethod = "printSysCROperand"; + let ParserMatchClass = SysCRAsmOperand; + let OperandType = "OPERAND_IMMEDIATE"; +} + +def sysp_crm_op : Operand<i32>, ImmLeaf<i32, [{ + return Imm >= 0 && Imm <= 7; +}]> { + let PrintMethod = "printSysCROperand"; + let ParserMatchClass = SysCRAsmOperand; + let OperandType = "OPERAND_IMMEDIATE"; +} + class SystemXtI<bit L, string asm> : RtSystemI<L, (outs), (ins imm0_7:$op1, sys_cr_op:$Cn, sys_cr_op:$Cm, imm0_7:$op2, GPR64:$Rt), @@ -13279,7 +13303,8 @@ class BaseSYSPEncoding<bit L, string asm, string operands, dag outputs, dag inpu } class SystemPXtI<bit L, string asm> : BaseSYSPEncoding<L, asm, "\t$op1, $Cn, $Cm, $op2, $Rt", (outs), - (ins imm0_7:$op1, sys_cr_op:$Cn, sys_cr_op:$Cm, imm0_7:$op2, XSeqPairClassOperand:$Rt)>; + (ins sysp_op1:$op1, sysp_crn_op:$Cn, sysp_crm_op:$Cm, imm0_7:$op2, + XSeqPairClassOperand:$Rt)>; //---------------------------------------------------------------------------- // 2023 Armv9.5 Extensions diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.td b/llvm/lib/Target/AArch64/AArch64InstrInfo.td index 0abd3fd1da6bf..70bc9537cef02 100644 --- a/llvm/lib/Target/AArch64/AArch64InstrInfo.td +++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.td @@ -11453,11 +11453,14 @@ let Predicates = [HasRCPC3, HasNEON] in { //===----------------------------------------------------------------------===// // 128-bit System Instructions (FEAT_SYSINSTR128) //===----------------------------------------------------------------------===// -def SYSPxt : SystemPXtI<0, "sysp">; +def SYSPxt : SystemPXtI<0, "sysp"> { + let DecoderMethod = "DecodeSyspInstruction"; +} def SYSPxt_XZR : BaseSystemI<0, (outs), - (ins imm0_7:$op1, sys_cr_op:$Cn, sys_cr_op:$Cm, imm0_7:$op2, SyspXzrPairOperand:$xzr_pair), + (ins sysp_op1:$op1, sysp_crn_op:$Cn, sysp_crm_op:$Cm, imm0_7:$op2, + SyspXzrPairOperand:$xzr_pair), "sysp", "\t$op1, $Cn, $Cm, $op2, $xzr_pair">, Sched<[WriteSys]> { @@ -11483,7 +11486,8 @@ def SYSPxt_XZR } def : InstAlias<"sysp $op1, $Cn, $Cm, $op2", - (SYSPxt_XZR imm0_7:$op1, sys_cr_op:$Cn, sys_cr_op:$Cm, imm0_7:$op2, XZR)>; + (SYSPxt_XZR sysp_op1:$op1, sysp_crn_op:$Cn, sysp_crm_op:$Cm, + imm0_7:$op2, XZR)>; //--- // 128-bit System Registers (FEAT_SYSREG128) diff --git a/llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp b/llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp index 8fa1913ce24e5..ef0f9cb515d0b 100644 --- a/llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp +++ b/llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp @@ -1395,6 +1395,10 @@ static DecodeStatus DecodeSyspXzrInstruction(MCInst &Inst, uint32_t insn, unsigned CRm = fieldFromInstruction(insn, 8, 4); unsigned op2 = fieldFromInstruction(insn, 5, 3); unsigned Rt = fieldFromInstruction(insn, 0, 5); + + if (op1 > 6 || (CRn != 8 && CRn != 9) || CRm > 7 || op2 > 7) + return Fail; + if (Rt != 0b11111) return Fail; @@ -1408,6 +1412,27 @@ static DecodeStatus DecodeSyspXzrInstruction(MCInst &Inst, uint32_t insn, return Success; } +static DecodeStatus DecodeSyspInstruction(MCInst &Inst, uint32_t insn, + uint64_t Addr, + const MCDisassembler *Decoder) { + unsigned op1 = fieldFromInstruction(insn, 16, 3); + unsigned CRn = fieldFromInstruction(insn, 12, 4); + unsigned CRm = fieldFromInstruction(insn, 8, 4); + unsigned op2 = fieldFromInstruction(insn, 5, 3); + unsigned Rt = fieldFromInstruction(insn, 0, 5); + + if (op1 > 6 || (CRn != 8 && CRn != 9) || CRm > 7 || op2 > 7) + return Fail; + + Inst.addOperand(MCOperand::createImm(op1)); + Inst.addOperand(MCOperand::createImm(CRn)); + Inst.addOperand(MCOperand::createImm(CRm)); + Inst.addOperand(MCOperand::createImm(op2)); + DecodeXSeqPairsClassRegisterClass(Inst, Rt, Addr, Decoder); + + return Success; +} + static DecodeStatus DecodeSVELogicalImmInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr, const MCDisassembler *Decoder) { diff --git a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp index 2fe162f930fdf..05d23f3055130 100644 --- a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp +++ b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp @@ -1152,6 +1152,14 @@ bool AArch64InstPrinter::printSyspAlias(const MCInst *MI, unsigned CmVal = Cm.getImm(); unsigned Op2Val = Op2.getImm(); + // Early checks for invalid SYSP aliases + // Op1 == 0..6 + // Op2 == 0..7 + // Cm == 0..7 + // Cn == 8 or 9 + if (Op1Val > 6 || Op2Val > 7 || CmVal > 7 || (CnVal != 8 && CnVal != 9)) + return false; + uint16_t Encoding = Op2Val; Encoding |= CmVal << 3; Encoding |= CnVal << 7; diff --git a/llvm/test/MC/AArch64/armv9-sysp-diagnostics.s b/llvm/test/MC/AArch64/armv9-sysp-diagnostics.s index 8b466c10b0aa7..51bb307912fef 100644 --- a/llvm/test/MC/AArch64/armv9-sysp-diagnostics.s +++ b/llvm/test/MC/AArch64/armv9-sysp-diagnostics.s @@ -7,22 +7,21 @@ // registers with 128-bit formats (op0, op1, Cn, Cm, op2) // For sysp, op0 is 0 -sysp #0, c2, c0, #0, x0, x2 +sysp #0, c8, c0, #0, x0, x2 // ERRORS: error: expected second odd register of a consecutive same-size even/odd register pair -sysp #0, c2, c0, #0, x0 +sysp #0, c8, c0, #0, x0 // ERRORS: error: expected comma -sysp #0, c2, c0, #0, x1, x2 +sysp #0, c8, c0, #0, x1, x2 // ERRORS: error: expected first even register of a consecutive same-size even/odd register pair -sysp #0, c2, c0, #0, x31, x0 +sysp #0, c8, c0, #0, x31, x0 // ERRORS: error: xzr must be followed by xzr -sysp #0, c2, c0, #0, xzr, x30 +sysp #0, c8, c0, #0, xzr, x30 // ERRORS: error: xzr must be followed by xzr -sysp #0, c2, c0, #0, xzr +sysp #0, c8, c0, #0, xzr // ERRORS: error: expected comma -sysp #0, c2, c0, #0, xzr, +sysp #0, c8, c0, #0, xzr, // ERRORS: error: expected register operand - tlbip RVAE3IS // ERRORS: error: expected comma tlbip RVAE3IS, diff --git a/llvm/test/MC/AArch64/armv9-sysp-invalid.s b/llvm/test/MC/AArch64/armv9-sysp-invalid.s new file mode 100644 index 0000000000000..248d5ccc5056a --- /dev/null +++ b/llvm/test/MC/AArch64/armv9-sysp-invalid.s @@ -0,0 +1,20 @@ +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+d128 < %s \ +// RUN: | llvm-objdump -d --mattr=+d128 --no-print-imm-hex - \ +// RUN: | FileCheck %s --check-prefix=DISASM + +// Ensure invalid SYSP encodings are not printed as TLBIP aliases. + +// op1 = 7 (outside architecturally valid SYSP range for op1) +// Cn = 8, Cm = 0, op2 = 0, Rt = 0 (x0, x1) +.inst 0xd54f8000 + +// Cn = 0 (outside architecturally valid SYSP range for Cn) +.inst 0xd5480000 + +// Cm = 8 (outside architecturally valid SYSP range for Cm) +.inst 0xd5488800 + +// DISASM-NOT: tlbip +// DISASM: <unknown> +// DISASM: <unknown> +// DISASM: <unknown> diff --git a/llvm/test/MC/AArch64/armv9a-sysp.s b/llvm/test/MC/AArch64/armv9a-sysp.s index f1e039f3e8770..349f75eb95424 100644 --- a/llvm/test/MC/AArch64/armv9a-sysp.s +++ b/llvm/test/MC/AArch64/armv9a-sysp.s @@ -13,150 +13,150 @@ // registers with 128-bit formats (op0, op1, Cn, Cm, op2) // For sysp, op0 is 0 -sysp #0, c2, c0, #0, x0, x1// TTBR0_EL1 3 0 2 0 0 -// CHECK-INST: sysp #0, c2, c0, #0, x0, x1 -// CHECK-ENCODING: encoding: [0x00,0x20,0x48,0xd5] +sysp #0, c8, c0, #0, x0, x1 +// CHECK-INST: sysp #0, c8, c0, #0, x0, x1 +// CHECK-ENCODING: encoding: [0x00,0x80,0x48,0xd5] -sysp #0, c2, c0, #1, x0, x1// TTBR1_EL1 3 0 2 0 1 -// CHECK-INST: sysp #0, c2, c0, #1, x0, x1 -// CHECK-ENCODING: encoding: [0x20,0x20,0x48,0xd5] +sysp #0, c8, c0, #1, x0, x1 +// CHECK-INST: sysp #0, c8, c0, #1, x0, x1 +// CHECK-ENCODING: encoding: [0x20,0x80,0x48,0xd5] -sysp #0, c7, c4, #0, x0, x1// PAR_EL1 3 0 7 4 0 -// CHECK-INST: sysp #0, c7, c4, #0, x0, x1 -// CHECK-ENCODING: encoding: [0x00,0x74,0x48,0xd5] +sysp #0, c8, c4, #0, x0, x1 +// CHECK-INST: sysp #0, c8, c4, #0, x0, x1 +// CHECK-ENCODING: encoding: [0x00,0x84,0x48,0xd5] -sysp #0, c13, c0, #3, x0, x1 // RCWSMASK_EL1 3 0 13 0 3 -// CHECK-INST: sysp #0, c13, c0, #3, x0, x1 -// CHECK-ENCODING: encoding: [0x60,0xd0,0x48,0xd5] +sysp #0, c8, c0, #3, x0, x1 +// CHECK-INST: sysp #0, c8, c0, #3, x0, x1 +// CHECK-ENCODING: encoding: [0x60,0x80,0x48,0xd5] -sysp #0, c13, c0, #6, x0, x1 // RCWMASK_EL1 3 0 13 0 6 -// CHECK-INST: sysp #0, c13, c0, #6, x0, x1 -// CHECK-ENCODING: encoding: [0xc0,0xd0,0x48,0xd5] +sysp #0, c8, c0, #6, x0, x1 +// CHECK-INST: sysp #0, c8, c0, #6, x0, x1 +// CHECK-ENCODING: encoding: [0xc0,0x80,0x48,0xd5] -sysp #4, c2, c0, #0, x0, x1// TTBR0_EL2 3 4 2 0 0 -// CHECK-INST: sysp #4, c2, c0, #0, x0, x1 -// CHECK-ENCODING: encoding: [0x00,0x20,0x4c,0xd5] +sysp #4, c8, c0, #0, x0, x1 +// CHECK-INST: sysp #4, c8, c0, #0, x0, x1 +// CHECK-ENCODING: encoding: [0x00,0x80,0x4c,0xd5] -sysp #4, c2, c0, #1, x0, x1// TTBR1_EL2 3 4 2 0 1 -// CHECK-INST: sysp #4, c2, c0, #1, x0, x1 -// CHECK-ENCODING: encoding: [0x20,0x20,0x4c,0xd5] +sysp #4, c8, c0, #3, x0, x1 +// CHECK-INST: sysp #4, c8, c0, #3, x0, x1 +// CHECK-ENCODING: encoding: [0x60,0x80,0x4c,0xd5] -sysp #4, c2, c1, #0, x0, x1// VTTBR_EL2 3 4 2 1 0 -// CHECK-INST: sysp #4, c2, c1, #0, x0, x1 -// CHECK-ENCODING: encoding: [0x00,0x21,0x4c,0xd5] +sysp #4, c8, c1, #0, x0, x1 +// CHECK-INST: sysp #4, c8, c1, #0, x0, x1 +// CHECK-ENCODING: encoding: [0x00,0x81,0x4c,0xd5] -sysp #0, c2, c0, #0, x0, x1 -// CHECK-INST: sysp #0, c2, c0, #0, x0, x1 -// CHECK-ENCODING: encoding: [0x00,0x20,0x48,0xd5] +sysp #0, c8, c0, #0, x0, x1 +// CHECK-INST: sysp #0, c8, c0, #0, x0, x1 +// CHECK-ENCODING: encoding: [0x00,0x80,0x48,0xd5] -sysp #0, c2, c0, #1, x0, x1 -// CHECK-INST: sysp #0, c2, c0, #1, x0, x1 -// CHECK-ENCODING: encoding: [0x20,0x20,0x48,0xd5] +sysp #0, c8, c0, #1, x0, x1 +// CHECK-INST: sysp #0, c8, c0, #1, x0, x1 +// CHECK-ENCODING: encoding: [0x20,0x80,0x48,0xd5] -sysp #0, c7, c4, #0, x0, x1 -// CHECK-INST: sysp #0, c7, c4, #0, x0, x1 -// CHECK-ENCODING: encoding: [0x00,0x74,0x48,0xd5] +sysp #0, c8, c4, #0, x0, x1 +// CHECK-INST: sysp #0, c8, c4, #0, x0, x1 +// CHECK-ENCODING: encoding: [0x00,0x84,0x48,0xd5] -sysp #0, c13, c0, #3, x0, x1 -// CHECK-INST: sysp #0, c13, c0, #3, x0, x1 -// CHECK-ENCODING: encoding: [0x60,0xd0,0x48,0xd5] +sysp #0, c8, c0, #3, x0, x1 +// CHECK-INST: sysp #0, c8, c0, #3, x0, x1 +// CHECK-ENCODING: encoding: [0x60,0x80,0x48,0xd5] -sysp #0, c13, c0, #6, x0, x1 -// CHECK-INST: sysp #0, c13, c0, #6, x0, x1 -// CHECK-ENCODING: encoding: [0xc0,0xd0,0x48,0xd5] +sysp #0, c8, c0, #6, x0, x1 +// CHECK-INST: sysp #0, c8, c0, #6, x0, x1 +// CHECK-ENCODING: encoding: [0xc0,0x80,0x48,0xd5] -sysp #4, c2, c0, #0, x0, x1 -// CHECK-INST: sysp #4, c2, c0, #0, x0, x1 -// CHECK-ENCODING: encoding: [0x00,0x20,0x4c,0xd5] +sysp #4, c8, c0, #0, x0, x1 +// CHECK-INST: sysp #4, c8, c0, #0, x0, x1 +// CHECK-ENCODING: encoding: [0x00,0x80,0x4c,0xd5] -sysp #4, c2, c0, #1, x0, x1 -// CHECK-INST: sysp #4, c2, c0, #1, x0, x1 -// CHECK-ENCODING: encoding: [0x20,0x20,0x4c,0xd5] +sysp #4, c8, c0, #3, x0, x1 +// CHECK-INST: sysp #4, c8, c0, #3, x0, x1 +// CHECK-ENCODING: encoding: [0x60,0x80,0x4c,0xd5] -sysp #4, c2, c1, #0, x0, x1 -// CHECK-INST: sysp #4, c2, c1, #0, x0, x1 -// CHECK-ENCODING: encoding: [0x00,0x21,0x4c,0xd5] +sysp #4, c8, c1, #0, x0, x1 +// CHECK-INST: sysp #4, c8, c1, #0, x0, x1 +// CHECK-ENCODING: encoding: [0x00,0x81,0x4c,0xd5] -sysp #0, c2, c0, #0, x0, x1 -// CHECK-INST: sysp #0, c2, c0, #0, x0, x1 -// CHECK-ENCODING: encoding: [0x00,0x20,0x48,0xd5] +sysp #0, c8, c0, #0, x0, x1 +// CHECK-INST: sysp #0, c8, c0, #0, x0, x1 +// CHECK-ENCODING: encoding: [0x00,0x80,0x48,0xd5] -sysp #0, c2, c0, #0, x2, x3 -// CHECK-INST: sysp #0, c2, c0, #0, x2, x3 -// CHECK-ENCODING: encoding: [0x02,0x20,0x48,0xd5] +sysp #0, c8, c0, #0, x2, x3 +// CHECK-INST: sysp #0, c8, c0, #0, x2, x3 +// CHECK-ENCODING: encoding: [0x02,0x80,0x48,0xd5] -sysp #0, c2, c0, #0, x4, x5 -// CHECK-INST: sysp #0, c2, c0, #0, x4, x5 -// CHECK-ENCODING: encoding: [0x04,0x20,0x48,0xd5] +sysp #0, c8, c0, #0, x4, x5 +// CHECK-INST: sysp #0, c8, c0, #0, x4, x5 +// CHECK-ENCODING: encoding: [0x04,0x80,0x48,0xd5] -sysp #0, c2, c0, #0, x6, x7 -// CHECK-INST: sysp #0, c2, c0, #0, x6, x7 -// CHECK-ENCODING: encoding: [0x06,0x20,0x48,0xd5] +sysp #0, c8, c0, #0, x6, x7 +// CHECK-INST: sysp #0, c8, c0, #0, x6, x7 +// CHECK-ENCODING: encoding: [0x06,0x80,0x48,0xd5] -sysp #0, c2, c0, #0, x8, x9 -// CHECK-INST: sysp #0, c2, c0, #0, x8, x9 -// CHECK-ENCODING: encoding: [0x08,0x20,0x48,0xd5] +sysp #0, c8, c0, #0, x8, x9 +// CHECK-INST: sysp #0, c8, c0, #0, x8, x9 +// CHECK-ENCODING: encoding: [0x08,0x80,0x48,0xd5] -sysp #0, c2, c0, #0, x10, x11 -// CHECK-INST: sysp #0, c2, c0, #0, x10, x11 -// CHECK-ENCODING: encoding: [0x0a,0x20,0x48,0xd5] +sysp #0, c8, c0, #0, x10, x11 +// CHECK-INST: sysp #0, c8, c0, #0, x10, x11 +// CHECK-ENCODING: encoding: [0x0a,0x80,0x48,0xd5] -sysp #0, c2, c0, #0, x12, x13 -// CHECK-INST: sysp #0, c2, c0, #0, x12, x13 -// CHECK-ENCODING: encoding: [0x0c,0x20,0x48,0xd5] +sysp #0, c8, c0, #0, x12, x13 +// CHECK-INST: sysp #0, c8, c0, #0, x12, x13 +// CHECK-ENCODING: encoding: [0x0c,0x80,0x48,0xd5] -sysp #0, c2, c0, #0, x14, x15 -// CHECK-INST: sysp #0, c2, c0, #0, x14, x15 -// CHECK-ENCODING: encoding: [0x0e,0x20,0x48,0xd5] +sysp #0, c8, c0, #0, x14, x15 +// CHECK-INST: sysp #0, c8, c0, #0, x14, x15 +// CHECK-ENCODING: encoding: [0x0e,0x80,0x48,0xd5] -sysp #0, c2, c0, #0, x16, x17 -// CHECK-INST: sysp #0, c2, c0, #0, x16, x17 -// CHECK-ENCODING: encoding: [0x10,0x20,0x48,0xd5] +sysp #0, c8, c0, #0, x16, x17 +// CHECK-INST: sysp #0, c8, c0, #0, x16, x17 +// CHECK-ENCODING: encoding: [0x10,0x80,0x48,0xd5] -sysp #0, c2, c0, #0, x18, x19 -// CHECK-INST: sysp #0, c2, c0, #0, x18, x19 -// CHECK-ENCODING: encoding: [0x12,0x20,0x48,0xd5] +sysp #0, c8, c0, #0, x18, x19 +// CHECK-INST: sysp #0, c8, c0, #0, x18, x19 +// CHECK-ENCODING: encoding: [0x12,0x80,0x48,0xd5] -sysp #0, c2, c0, #0, x20, x21 -// CHECK-INST: sysp #0, c2, c0, #0, x20, x21 -// CHECK-ENCODING: encoding: [0x14,0x20,0x48,0xd5] +sysp #0, c8, c0, #0, x20, x21 +// CHECK-INST: sysp #0, c8, c0, #0, x20, x21 +// CHECK-ENCODING: encoding: [0x14,0x80,0x48,0xd5] -sysp #0, c2, c0, #0, x22, x23 -// CHECK-INST: sysp #0, c2, c0, #0, x22, x23 -// CHECK-ENCODING: encoding: [0x16,0x20,0x48,0xd5] +sysp #0, c8, c0, #0, x22, x23 +// CHECK-INST: sysp #0, c8, c0, #0, x22, x23 +// CHECK-ENCODING: encoding: [0x16,0x80,0x48,0xd5] -sysp #0, c2, c0, #0, x24, x25 -// CHECK-INST: sysp #0, c2, c0, #0, x24, x25 -// CHECK-ENCODING: encoding: [0x18,0x20,0x48,0xd5] +sysp #0, c8, c0, #0, x24, x25 +// CHECK-INST: sysp #0, c8, c0, #0, x24, x25 +// CHECK-ENCODING: encoding: [0x18,0x80,0x48,0xd5] -sysp #0, c2, c0, #0, x26, x27 -// CHECK-INST: sysp #0, c2, c0, #0, x26, x27 -// CHECK-ENCODING: encoding: [0x1a,0x20,0x48,0xd5] +sysp #0, c8, c0, #0, x26, x27 +// CHECK-INST: sysp #0, c8, c0, #0, x26, x27 +// CHECK-ENCODING: encoding: [0x1a,0x80,0x48,0xd5] -sysp #0, c2, c0, #0, x28, x29 -// CHECK-INST: sysp #0, c2, c0, #0, x28, x29 -// CHECK-ENCODING: encoding: [0x1c,0x20,0x48,0xd5] +sysp #0, c8, c0, #0, x28, x29 +// CHECK-INST: sysp #0, c8, c0, #0, x28, x29 +// CHECK-ENCODING: encoding: [0x1c,0x80,0x48,0xd5] -sysp #0, c2, c0, #0, x30, x31 -// CHECK-INST: sysp #0, c2, c0, #0, x30, xzr -// CHECK-ENCODING: encoding: [0x1e,0x20,0x48,0xd5] +sysp #0, c8, c0, #0, x30, x31 +// CHECK-INST: sysp #0, c8, c0, #0, x30, xzr +// CHECK-ENCODING: encoding: [0x1e,0x80,0x48,0xd5] -sysp #0, c2, c0, #0, x31, x31 -// CHECK-INST: sysp #0, c2, c0, #0 -// CHECK-ENCODING: encoding: [0x1f,0x20,0x48,0xd5] +sysp #0, c8, c0, #0, x31, x31 +// CHECK-INST: sysp #0, c8, c0, #0 +// CHECK-ENCODING: encoding: [0x1f,0x80,0x48,0xd5] -sysp #0, c2, c0, #0, xzr, xzr -// CHECK-INST: sysp #0, c2, c0, #0 -// CHECK-ENCODING: encoding: [0x1f,0x20,0x48,0xd5] +sysp #0, c8, c0, #0, xzr, xzr +// CHECK-INST: sysp #0, c8, c0, #0 +// CHECK-ENCODING: encoding: [0x1f,0x80,0x48,0xd5] -sysp #0, c2, c0, #0, x31, xzr -// CHECK-INST: sysp #0, c2, c0, #0 -// CHECK-ENCODING: encoding: [0x1f,0x20,0x48,0xd5] +sysp #0, c8, c0, #0, x31, xzr +// CHECK-INST: sysp #0, c8, c0, #0 +// CHECK-ENCODING: encoding: [0x1f,0x80,0x48,0xd5] -sysp #0, c2, c0, #0, xzr, x31 -// CHECK-INST: sysp #0, c2, c0, #0 -// CHECK-ENCODING: encoding: [0x1f,0x20,0x48,0xd5] +sysp #0, c8, c0, #0, xzr, x31 +// CHECK-INST: sysp #0, c8, c0, #0 +// CHECK-ENCODING: encoding: [0x1f,0x80,0x48,0xd5] -sysp #0, c2, c0, #0 -// CHECK-INST: sysp #0, c2, c0, #0 -// CHECK-ENCODING: encoding: [0x1f,0x20,0x48,0xd5] +sysp #0, c8, c0, #0 +// CHECK-INST: sysp #0, c8, c0, #0 +// CHECK-ENCODING: encoding: [0x1f,0x80,0x48,0xd5] >From 767465c26ef761da80d53482814f790d40472e1f Mon Sep 17 00:00:00 2001 From: Jonathan Thackray <[email protected]> Date: Thu, 5 Mar 2026 12:32:15 +0000 Subject: [PATCH 2/3] fixup! Address Marian's PR comments: use imm0_6 predicate --- llvm/lib/Target/AArch64/AArch64InstrFormats.td | 18 +++++++++--------- llvm/lib/Target/AArch64/AArch64InstrInfo.td | 4 ++-- 2 files changed, 11 insertions(+), 11 deletions(-) diff --git a/llvm/lib/Target/AArch64/AArch64InstrFormats.td b/llvm/lib/Target/AArch64/AArch64InstrFormats.td index 2f92c02bbc1f4..42c2cccfb75ba 100644 --- a/llvm/lib/Target/AArch64/AArch64InstrFormats.td +++ b/llvm/lib/Target/AArch64/AArch64InstrFormats.td @@ -943,6 +943,7 @@ def Imm0_1Operand : AsmImmRange<0, 1>; def Imm1_1Operand : AsmImmRange<1, 1>; def Imm0_3Operand : AsmImmRange<0, 3>; def Imm1_3Operand : AsmImmRange<1, 3>; +def Imm0_6Operand : AsmImmRange<0, 6>; def Imm0_7Operand : AsmImmRange<0, 7>; def Imm1_7Operand : AsmImmRange<1, 7>; def Imm0_15Operand : AsmImmRange<0, 15>; @@ -1176,6 +1177,13 @@ def imm0_15 : Operand<i64>, ImmLeaf<i64, [{ let ParserMatchClass = Imm0_15Operand; } +// imm0_6 predicate - True if the immediate is in the range [0,6] +def imm0_6 : Operand<i64>, ImmLeaf<i64, [{ + return ((uint64_t)Imm) < 7; +}]> { + let ParserMatchClass = Imm0_6Operand; +} + // imm0_7 predicate - True if the immediate is in the range [0,7] def imm0_7 : Operand<i64>, ImmLeaf<i64, [{ return ((uint64_t)Imm) < 8; @@ -2122,14 +2130,6 @@ def sys_cr_op : Operand<i32> { let OperandType = "OPERAND_IMMEDIATE"; } -// SYSP operands are more restricted than generic system CR/imm fields. -def sysp_op1 : Operand<i64>, ImmLeaf<i64, [{ - return Imm >= 0 && Imm <= 6; -}]> { - let ParserMatchClass = Imm0_7Operand; - let OperandType = "OPERAND_IMMEDIATE"; -} - def sysp_crn_op : Operand<i32>, ImmLeaf<i32, [{ return Imm == 8 || Imm == 9; }]> { @@ -13303,7 +13303,7 @@ class BaseSYSPEncoding<bit L, string asm, string operands, dag outputs, dag inpu } class SystemPXtI<bit L, string asm> : BaseSYSPEncoding<L, asm, "\t$op1, $Cn, $Cm, $op2, $Rt", (outs), - (ins sysp_op1:$op1, sysp_crn_op:$Cn, sysp_crm_op:$Cm, imm0_7:$op2, + (ins imm0_6:$op1, sysp_crn_op:$Cn, sysp_crm_op:$Cm, imm0_7:$op2, XSeqPairClassOperand:$Rt)>; //---------------------------------------------------------------------------- diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.td b/llvm/lib/Target/AArch64/AArch64InstrInfo.td index 70bc9537cef02..5f0722dee39b6 100644 --- a/llvm/lib/Target/AArch64/AArch64InstrInfo.td +++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.td @@ -11459,7 +11459,7 @@ def SYSPxt : SystemPXtI<0, "sysp"> { def SYSPxt_XZR : BaseSystemI<0, (outs), - (ins sysp_op1:$op1, sysp_crn_op:$Cn, sysp_crm_op:$Cm, imm0_7:$op2, + (ins imm0_6:$op1, sysp_crn_op:$Cn, sysp_crm_op:$Cm, imm0_7:$op2, SyspXzrPairOperand:$xzr_pair), "sysp", "\t$op1, $Cn, $Cm, $op2, $xzr_pair">, Sched<[WriteSys]> @@ -11486,7 +11486,7 @@ def SYSPxt_XZR } def : InstAlias<"sysp $op1, $Cn, $Cm, $op2", - (SYSPxt_XZR sysp_op1:$op1, sysp_crn_op:$Cn, sysp_crm_op:$Cm, + (SYSPxt_XZR imm0_6:$op1, sysp_crn_op:$Cn, sysp_crm_op:$Cm, imm0_7:$op2, XZR)>; //--- >From 8e6951b3e89f6df485d27b4086fad13b3ff9d75e Mon Sep 17 00:00:00 2001 From: Jonathan Thackray <[email protected]> Date: Thu, 5 Mar 2026 14:41:46 +0000 Subject: [PATCH 3/3] fixup! Templatise bounds checking and improve tests --- .../lib/Target/AArch64/AArch64InstrFormats.td | 17 ++++++++++++----- .../AArch64/AsmParser/AArch64AsmParser.cpp | 18 ++++++++++++++++++ .../MCTargetDesc/AArch64InstPrinter.cpp | 8 -------- llvm/test/MC/AArch64/armv9-sysp-diagnostics.s | 19 +++++++++++++++---- 4 files changed, 45 insertions(+), 17 deletions(-) diff --git a/llvm/lib/Target/AArch64/AArch64InstrFormats.td b/llvm/lib/Target/AArch64/AArch64InstrFormats.td index 42c2cccfb75ba..891a5f2446ee9 100644 --- a/llvm/lib/Target/AArch64/AArch64InstrFormats.td +++ b/llvm/lib/Target/AArch64/AArch64InstrFormats.td @@ -2119,14 +2119,21 @@ class MSRpstateImm0_1 } // SYS and SYSL generic system instructions. -def SysCRAsmOperand : AsmOperandClass { - let Name = "SysCR"; +class SysCRAsmOperand<int Low, int High> : AsmOperandClass { + let Name = "SysCR" # Low # "_" # High; + let RenderMethod = "addSysCROperands"; let ParserMethod = "tryParseSysCROperand"; + let PredicateMethod = "isSysCRInRange<" # Low # "," # High # ">"; + let DiagnosticType = "InvalidSysCR" # Low # "_" # High; } +def SysCRm0_7AsmOperand : SysCRAsmOperand<0, 7>; +def SysCRn8_9AsmOperand : SysCRAsmOperand<8, 9>; +def SysCR0_15AsmOperand : SysCRAsmOperand<0, 15>; + def sys_cr_op : Operand<i32> { let PrintMethod = "printSysCROperand"; - let ParserMatchClass = SysCRAsmOperand; + let ParserMatchClass = SysCR0_15AsmOperand; let OperandType = "OPERAND_IMMEDIATE"; } @@ -2134,7 +2141,7 @@ def sysp_crn_op : Operand<i32>, ImmLeaf<i32, [{ return Imm == 8 || Imm == 9; }]> { let PrintMethod = "printSysCROperand"; - let ParserMatchClass = SysCRAsmOperand; + let ParserMatchClass = SysCRn8_9AsmOperand; let OperandType = "OPERAND_IMMEDIATE"; } @@ -2142,7 +2149,7 @@ def sysp_crm_op : Operand<i32>, ImmLeaf<i32, [{ return Imm >= 0 && Imm <= 7; }]> { let PrintMethod = "printSysCROperand"; - let ParserMatchClass = SysCRAsmOperand; + let ParserMatchClass = SysCRm0_7AsmOperand; let OperandType = "OPERAND_IMMEDIATE"; } diff --git a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp index 590da8f93873d..9bd8bd56dd484 100644 --- a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp +++ b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp @@ -1551,6 +1551,12 @@ class AArch64Operand : public MCParsedAsmOperand { return Kind == k_Token && getToken() == Str; } bool isSysCR() const { return Kind == k_SysCR; } + template <unsigned low, unsigned high> bool isSysCRInRange() const { + if (!isSysCR()) + return false; + unsigned Val = getSysCR(); + return Val >= low && Val <= high; + } bool isPrefetch() const { return Kind == k_Prefetch; } bool isPSBHint() const { return Kind == k_PSBHint; } bool isPHint() const { return Kind == k_PHint; } @@ -6293,6 +6299,8 @@ bool AArch64AsmParser::showMatchError(SMLoc Loc, unsigned ErrCode, return Error(Loc, "immediate must be an integer in range [0, 1]."); case Match_InvalidImm0_3: return Error(Loc, "immediate must be an integer in range [0, 3]."); + case Match_InvalidImm0_6: + return Error(Loc, "immediate must be an integer in range [0, 6]."); case Match_InvalidImm0_7: return Error(Loc, "immediate must be an integer in range [0, 7]."); case Match_InvalidImm0_15: @@ -6317,6 +6325,12 @@ bool AArch64AsmParser::showMatchError(SMLoc Loc, unsigned ErrCode, return Error(Loc, "immediate must be an integer in range [1, 64]."); case Match_InvalidImmM1_62: return Error(Loc, "immediate must be an integer in range [-1, 62]."); + case Match_InvalidSysCR0_7: + return Error(Loc, "expected cM operand where 0 <= M <= 7"); + case Match_InvalidSysCR8_9: + return Error(Loc, "expected cN operand where 8 <= N <= 9"); + case Match_InvalidSysCR0_15: + return Error(Loc, "expected cN operand where 0 <= N <= 15"); case Match_InvalidMemoryIndexedRange2UImm0: return Error(Loc, "vector select offset must be the immediate range 0:1."); case Match_InvalidMemoryIndexedRange2UImm1: @@ -7081,6 +7095,7 @@ bool AArch64AsmParser::matchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, case Match_InvalidImm0_0: case Match_InvalidImm0_1: case Match_InvalidImm0_3: + case Match_InvalidImm0_6: case Match_InvalidImm0_7: case Match_InvalidImm0_15: case Match_InvalidImm0_31: @@ -7093,6 +7108,9 @@ bool AArch64AsmParser::matchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, case Match_InvalidImm1_32: case Match_InvalidImm1_64: case Match_InvalidImmM1_62: + case Match_InvalidSysCR0_7: + case Match_InvalidSysCR8_9: + case Match_InvalidSysCR0_15: case Match_InvalidMemoryIndexedRange2UImm0: case Match_InvalidMemoryIndexedRange2UImm1: case Match_InvalidMemoryIndexedRange2UImm2: diff --git a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp index 05d23f3055130..2fe162f930fdf 100644 --- a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp +++ b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp @@ -1152,14 +1152,6 @@ bool AArch64InstPrinter::printSyspAlias(const MCInst *MI, unsigned CmVal = Cm.getImm(); unsigned Op2Val = Op2.getImm(); - // Early checks for invalid SYSP aliases - // Op1 == 0..6 - // Op2 == 0..7 - // Cm == 0..7 - // Cn == 8 or 9 - if (Op1Val > 6 || Op2Val > 7 || CmVal > 7 || (CnVal != 8 && CnVal != 9)) - return false; - uint16_t Encoding = Op2Val; Encoding |= CmVal << 3; Encoding |= CnVal << 7; diff --git a/llvm/test/MC/AArch64/armv9-sysp-diagnostics.s b/llvm/test/MC/AArch64/armv9-sysp-diagnostics.s index 51bb307912fef..4e0ba1bbb1772 100644 --- a/llvm/test/MC/AArch64/armv9-sysp-diagnostics.s +++ b/llvm/test/MC/AArch64/armv9-sysp-diagnostics.s @@ -9,16 +9,22 @@ sysp #0, c8, c0, #0, x0, x2 // ERRORS: error: expected second odd register of a consecutive same-size even/odd register pair -sysp #0, c8, c0, #0, x0 -// ERRORS: error: expected comma sysp #0, c8, c0, #0, x1, x2 // ERRORS: error: expected first even register of a consecutive same-size even/odd register pair sysp #0, c8, c0, #0, x31, x0 // ERRORS: error: xzr must be followed by xzr sysp #0, c8, c0, #0, xzr, x30 // ERRORS: error: xzr must be followed by xzr -sysp #0, c8, c0, #0, xzr -// ERRORS: error: expected comma +sysp #7, c8, c0, #0, x0, x1 +// ERRORS: error: immediate must be an integer in range [0, 6]. +sysp #0, c7, c0, #0, x0, x1 +// ERRORS: error: expected cN operand where 8 <= N <= 9 +sysp #0, c10, c0, #0, x0, x1 +// ERRORS: error: expected cN operand where 8 <= N <= 9 +sysp #0, c8, c8, #0, x0, x1 +// ERRORS: error: expected cM operand where 0 <= M <= 7 +sysp #0, c8, c0, #8, x0, x1 +// ERRORS: error: immediate must be an integer in range [0, 7]. sysp #0, c8, c0, #0, xzr, // ERRORS: error: expected register operand @@ -32,3 +38,8 @@ tlbip IPAS2E1, x4, x8 // ERRORS: error: specified tlbip op requires a pair of registers tlbip RVAE3, x11, x11 // ERRORS: error: specified tlbip op requires a pair of registers + +sysp #0, c8, c0, #0, x0 +// ERRORS: error: expected comma +sysp #0, c8, c0, #0, xzr +// ERRORS: error: expected comma _______________________________________________ lldb-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
