https://github.com/ayushsahay1837 updated https://github.com/llvm/llvm-project/pull/196892
>From 4d412b50e40847b16ebb6b75f750869558f48a52 Mon Sep 17 00:00:00 2001 From: Ayush Sahay <[email protected]> Date: Sun, 10 May 2026 18:25:31 +0530 Subject: [PATCH 1/3] [lldb] Add Hexagon register layout to Scripted{Frame,Thread} Add support for handling register information for Hexagon in ScriptedFrame.get_register_info and ScriptedThread.get_register_info. --- .../python/templates/scripted_process.py | 484 ++++++++++++++++++ 1 file changed, 484 insertions(+) diff --git a/lldb/examples/python/templates/scripted_process.py b/lldb/examples/python/templates/scripted_process.py index 9a097fab4f803..7d36eb6b6f03c 100644 --- a/lldb/examples/python/templates/scripted_process.py +++ b/lldb/examples/python/templates/scripted_process.py @@ -363,6 +363,9 @@ def get_register_info(self): elif "arm" in self.arch or "thumb" in self.arch: self.register_info["sets"] = ["General Purpose Registers"] self.register_info["registers"] = ARM32_GPR + elif "hexagon" in self.arch: + self.register_info['sets'] = ['General Purpose Registers'] + self.register_info['registers'] = HEXAGON_GPR else: raise ValueError("Unknown architecture", self.arch) return self.register_info @@ -526,6 +529,9 @@ def get_register_info(self): elif "arm" in self.arch or "thumb" in self.arch: self.register_info["sets"] = ["General Purpose Registers"] self.register_info["registers"] = ARM32_GPR + elif "hexagon" in self.arch: + self.register_info['sets'] = ['General Purpose Registers'] + self.register_info['registers'] = HEXAGON_GPR else: raise ValueError("Unknown architecture", self.arch) return self.register_info @@ -1249,6 +1255,484 @@ def get_register_context(self): }, ] +HEXAGON_GPR = [ + { + "name": "r0", + "bitsize": 32, + "offset": 0, + "encoding": "uint", + "format": "hex", + "set": 0, + "gcc": 0, + "dwarf": 0, + }, + { + "name": "r1", + "bitsize": 32, + "offset": 4, + "encoding": "uint", + "format": "hex", + "set": 0, + "gcc": 0, + "dwarf": 0, + }, + { + "name": "r2", + "bitsize": 32, + "offset": 8, + "encoding": "uint", + "format": "hex", + "set": 0, + "gcc": 0, + "dwarf": 0, + }, + { + "name": "r3", + "bitsize": 32, + "offset": 12, + "encoding": "uint", + "format": "hex", + "set": 0, + "gcc": 0, + "dwarf": 0, + }, + { + "name": "r4", + "bitsize": 32, + "offset": 16, + "encoding": "uint", + "format": "hex", + "set": 0, + "gcc": 0, + "dwarf": 0, + }, + { + "name": "r5", + "bitsize": 32, + "offset": 20, + "encoding": "uint", + "format": "hex", + "set": 0, + "gcc": 0, + "dwarf": 0, + }, + { + "name": "r6", + "bitsize": 32, + "offset": 24, + "encoding": "uint", + "format": "hex", + "set": 0, + "gcc": 0, + "dwarf": 0, + }, + { + "name": "r7", + "bitsize": 32, + "offset": 28, + "encoding": "uint", + "format": "hex", + "set": 0, + "gcc": 0, + "dwarf": 0, + }, + { + "name": "r8", + "bitsize": 32, + "offset": 32, + "encoding": "uint", + "format": "hex", + "set": 0, + "gcc": 0, + "dwarf": 0, + }, + { + "name": "r9", + "bitsize": 32, + "offset": 36, + "encoding": "uint", + "format": "hex", + "set": 0, + "gcc": 0, + "dwarf": 0, + }, + { + "name": "r10", + "bitsize": 32, + "offset": 40, + "encoding": "uint", + "format": "hex", + "set": 0, + "gcc": 0, + "dwarf": 0, + }, + { + "name": "r11", + "bitsize": 32, + "offset": 44, + "encoding": "uint", + "format": "hex", + "set": 0, + "gcc": 0, + "dwarf": 0, + }, + { + "name": "r12", + "bitsize": 32, + "offset": 48, + "encoding": "uint", + "format": "hex", + "set": 0, + "gcc": 0, + "dwarf": 0, + }, + { + "name": "r13", + "bitsize": 32, + "offset": 52, + "encoding": "uint", + "format": "hex", + "set": 0, + "gcc": 0, + "dwarf": 0, + }, + { + "name": "r14", + "bitsize": 32, + "offset": 56, + "encoding": "uint", + "format": "hex", + "set": 0, + "gcc": 0, + "dwarf": 0, + }, + { + "name": "r15", + "bitsize": 32, + "offset": 60, + "encoding": "uint", + "format": "hex", + "set": 0, + "gcc": 0, + "dwarf": 0, + }, + { + "name": "r16", + "bitsize": 32, + "offset": 64, + "encoding": "uint", + "format": "hex", + "set": 0, + "gcc": 0, + "dwarf": 0, + }, + { + "name": "r17", + "bitsize": 32, + "offset": 68, + "encoding": "uint", + "format": "hex", + "set": 0, + "gcc": 0, + "dwarf": 0, + }, + { + "name": "r18", + "bitsize": 32, + "offset": 72, + "encoding": "uint", + "format": "hex", + "set": 0, + "gcc": 0, + "dwarf": 0, + }, + { + "name": "r19", + "bitsize": 32, + "offset": 76, + "encoding": "uint", + "format": "hex", + "set": 0, + "gcc": 0, + "dwarf": 0, + }, + { + "name": "r20", + "bitsize": 32, + "offset": 80, + "encoding": "uint", + "format": "hex", + "set": 0, + "gcc": 0, + "dwarf": 0, + }, + { + "name": "r21", + "bitsize": 32, + "offset": 84, + "encoding": "uint", + "format": "hex", + "set": 0, + "gcc": 0, + "dwarf": 0, + }, + { + "name": "r22", + "bitsize": 32, + "offset": 88, + "encoding": "uint", + "format": "hex", + "set": 0, + "gcc": 0, + "dwarf": 0, + }, + { + "name": "r23", + "bitsize": 32, + "offset": 92, + "encoding": "uint", + "format": "hex", + "set": 0, + "gcc": 0, + "dwarf": 0, + }, + { + "name": "r24", + "bitsize": 32, + "offset": 96, + "encoding": "uint", + "format": "hex", + "set": 0, + "gcc": 0, + "dwarf": 0, + }, + { + "name": "r25", + "bitsize": 32, + "offset": 100, + "encoding": "uint", + "format": "hex", + "set": 0, + "gcc": 0, + "dwarf": 0, + }, + { + "name": "r26", + "bitsize": 32, + "offset": 104, + "encoding": "uint", + "format": "hex", + "set": 0, + "gcc": 0, + "dwarf": 0, + }, + { + "name": "r27", + "bitsize": 32, + "offset": 108, + "encoding": "uint", + "format": "hex", + "set": 0, + "gcc": 0, + "dwarf": 0, + }, + { + "name": "r28", + "bitsize": 32, + "offset": 112, + "encoding": "uint", + "format": "hex", + "set": 0, + "gcc": 0, + "dwarf": 0, + }, + { + "name": "r29", + "bitsize": 32, + "offset": 116, + "encoding": "uint", + "format": "hex", + "set": 0, + "gcc": 0, + "dwarf": 0, + "alt-name": "sp", + }, + { + "name": "r30", + "bitsize": 32, + "offset": 120, + "encoding": "uint", + "format": "hex", + "set": 0, + "gcc": 0, + "dwarf": 0, + "alt-name": "fp", + }, + { + "name": "r31", + "bitsize": 32, + "offset": 124, + "encoding": "uint", + "format": "hex", + "set": 0, + "gcc": 0, + "dwarf": 0, + "alt-name": "lr", + }, + { + "name": "sa0", + "bitsize": 32, + "offset": 128, + "encoding": "uint", + "format": "hex", + "set": 0, + "gcc": 0, + "dwarf": 0, + }, + { + "name": "lc0", + "bitsize": 32, + "offset": 132, + "encoding": "uint", + "format": "hex", + "set": 0, + "gcc": 0, + "dwarf": 0, + }, + { + "name": "sa1", + "bitsize": 32, + "offset": 136, + "encoding": "uint", + "format": "hex", + "set": 0, + "gcc": 0, + "dwarf": 0, + }, + { + "name": "lc1", + "bitsize": 32, + "offset": 140, + "encoding": "uint", + "format": "hex", + "set": 0, + "gcc": 0, + "dwarf": 0, + }, + { + "name": "p3_0", + "bitsize": 32, + "offset": 144, + "encoding": "uint", + "format": "hex", + "set": 0, + "gcc": 0, + "dwarf": 0, + }, + { + "name": "m0", + "bitsize": 32, + "offset": 148, + "encoding": "uint", + "format": "hex", + "set": 0, + "gcc": 0, + "dwarf": 0, + }, + { + "name": "m1", + "bitsize": 32, + "offset": 152, + "encoding": "uint", + "format": "hex", + "set": 0, + "gcc": 0, + "dwarf": 0, + }, + { + "name": "usr", + "bitsize": 32, + "offset": 156, + "encoding": "uint", + "format": "hex", + "set": 0, + "gcc": 0, + "dwarf": 0, + }, + { + "name": "pc", + "bitsize": 32, + "offset": 160, + "encoding": "uint", + "format": "hex", + "set": 0, + "gcc": 0, + "dwarf": 0, + "generic": "pc", + "alt-name": "pc", + }, + { + "name": "ugp", + "bitsize": 32, + "offset": 164, + "encoding": "uint", + "format": "hex", + "set": 0, + "gcc": 0, + "dwarf": 0, + }, + { + "name": "gp", + "bitsize": 32, + "offset": 168, + "encoding": "uint", + "format": "hex", + "set": 0, + "gcc": 0, + "dwarf": 0, + }, + { + "name": "cs0", + "bitsize": 32, + "offset": 172, + "encoding": "uint", + "format": "hex", + "set": 0, + "gcc": 0, + "dwarf": 0, + }, + { + "name": "cs1", + "bitsize": 32, + "offset": 176, + "encoding": "uint", + "format": "hex", + "set": 0, + "gcc": 0, + "dwarf": 0, + }, + { + "name": "framelimit", + "bitsize": 32, + "offset": 180, + "encoding": "uint", + "format": "hex", + "set": 0, + "gcc": 0, + "dwarf": 0, + }, + { + "name": "framekey", + "bitsize": 32, + "offset": 184, + "encoding": "uint", + "format": "hex", + "set": 0, + "gcc": 0, + "dwarf": 0, + }, +] + INTEL64_GPR = [ { "name": "rax", >From db85397641aeaef28acfae336d718a86f5aed628 Mon Sep 17 00:00:00 2001 From: Ayush Sahay <[email protected]> Date: Mon, 11 May 2026 12:55:36 +0530 Subject: [PATCH 2/3] Fix formatting --- lldb/examples/python/templates/scripted_process.py | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/lldb/examples/python/templates/scripted_process.py b/lldb/examples/python/templates/scripted_process.py index 7d36eb6b6f03c..23afb1c74cb8c 100644 --- a/lldb/examples/python/templates/scripted_process.py +++ b/lldb/examples/python/templates/scripted_process.py @@ -364,8 +364,8 @@ def get_register_info(self): self.register_info["sets"] = ["General Purpose Registers"] self.register_info["registers"] = ARM32_GPR elif "hexagon" in self.arch: - self.register_info['sets'] = ['General Purpose Registers'] - self.register_info['registers'] = HEXAGON_GPR + self.register_info["sets"] = ['General Purpose Registers'] + self.register_info["registers"] = HEXAGON_GPR else: raise ValueError("Unknown architecture", self.arch) return self.register_info @@ -530,8 +530,8 @@ def get_register_info(self): self.register_info["sets"] = ["General Purpose Registers"] self.register_info["registers"] = ARM32_GPR elif "hexagon" in self.arch: - self.register_info['sets'] = ['General Purpose Registers'] - self.register_info['registers'] = HEXAGON_GPR + self.register_info["sets"] = ['General Purpose Registers'] + self.register_info["registers"] = HEXAGON_GPR else: raise ValueError("Unknown architecture", self.arch) return self.register_info >From 02683e75f3606d92c088efbac6e0b039b89265ab Mon Sep 17 00:00:00 2001 From: Ayush Sahay <[email protected]> Date: Mon, 11 May 2026 13:15:08 +0530 Subject: [PATCH 3/3] Fix formatting --- lldb/examples/python/templates/scripted_process.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/lldb/examples/python/templates/scripted_process.py b/lldb/examples/python/templates/scripted_process.py index 23afb1c74cb8c..af21c80e6896d 100644 --- a/lldb/examples/python/templates/scripted_process.py +++ b/lldb/examples/python/templates/scripted_process.py @@ -364,7 +364,7 @@ def get_register_info(self): self.register_info["sets"] = ["General Purpose Registers"] self.register_info["registers"] = ARM32_GPR elif "hexagon" in self.arch: - self.register_info["sets"] = ['General Purpose Registers'] + self.register_info["sets"] = ["General Purpose Registers"] self.register_info["registers"] = HEXAGON_GPR else: raise ValueError("Unknown architecture", self.arch) @@ -530,7 +530,7 @@ def get_register_info(self): self.register_info["sets"] = ["General Purpose Registers"] self.register_info["registers"] = ARM32_GPR elif "hexagon" in self.arch: - self.register_info["sets"] = ['General Purpose Registers'] + self.register_info["sets"] = ["General Purpose Registers"] self.register_info["registers"] = HEXAGON_GPR else: raise ValueError("Unknown architecture", self.arch) _______________________________________________ lldb-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
