================
@@ -813,9 +813,15 @@ def XSeqPairsClass : RegisterClass<"AArch64", [untyped],
64,
(add XSeqPairs)>{
let Size = 128;
}
+def SyspPairsClass : RegisterClass<"AArch64", [untyped], 64,
+ (add XSeqPairs, [XZR, XZR])>{
+ let Size = 128;
+ let isAllocatable = 0;
----------------
jthackray wrote:
Added a comment to explain why not.
https://github.com/llvm/llvm-project/pull/182410
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