https://github.com/jayfoad created https://github.com/llvm/llvm-project/pull/219442
None >From dc8c7e55be291e64787f44807aed31bf30a988f8 Mon Sep 17 00:00:00 2001 From: Jay Foad <[email protected]> Date: Fri, 28 Aug 2026 12:14:14 +0100 Subject: [PATCH] Fix typo "regsiter" in comments. NFC. --- .../Process/Utility/NativeProcessSoftwareSingleStep.cpp | 4 ++-- .../Process/minidump/RegisterContextMinidump_x86_64.cpp | 2 +- llvm/lib/Target/VE/VERegisterInfo.cpp | 2 +- llvm/lib/Target/X86/X86RegisterInfo.td | 2 +- .../AMDGPU/issue98474-need-live-out-undef-subregister-def.ll | 2 +- llvm/test/CodeGen/PowerPC/subreg-lanemasks.mir | 2 +- .../MC/Disassembler/PowerPC/ppc64-encoding-dfp-invalid.txt | 2 +- llvm/test/TableGen/ArtificialRegs.td | 2 +- 8 files changed, 9 insertions(+), 9 deletions(-) diff --git a/lldb/source/Plugins/Process/Utility/NativeProcessSoftwareSingleStep.cpp b/lldb/source/Plugins/Process/Utility/NativeProcessSoftwareSingleStep.cpp index e5aaef67b5e70..d71ac38ca1dc3 100644 --- a/lldb/source/Plugins/Process/Utility/NativeProcessSoftwareSingleStep.cpp +++ b/lldb/source/Plugins/Process/Utility/NativeProcessSoftwareSingleStep.cpp @@ -23,7 +23,7 @@ struct EmulatorBaton { NativeProcessProtocol &m_process; NativeRegisterContext &m_reg_context; - // eRegisterKindDWARF -> RegsiterValue + // eRegisterKindDWARF -> RegisterValue std::unordered_map<uint32_t, RegisterValue> m_register_values; EmulatorBaton(NativeProcessProtocol &process, @@ -55,7 +55,7 @@ static bool ReadRegisterCallback(EmulateInstruction *instruction, void *baton, return true; } - // The emulator only fill in the dwarf regsiter numbers (and in some case the + // The emulator only fill in the dwarf register numbers (and in some case the // generic register numbers). Get the full register info from the register // context based on the dwarf register numbers. const RegisterInfo *full_reg_info = diff --git a/lldb/source/Plugins/Process/minidump/RegisterContextMinidump_x86_64.cpp b/lldb/source/Plugins/Process/minidump/RegisterContextMinidump_x86_64.cpp index f305d1b7031d8..67d4817e4c6bf 100644 --- a/lldb/source/Plugins/Process/minidump/RegisterContextMinidump_x86_64.cpp +++ b/lldb/source/Plugins/Process/minidump/RegisterContextMinidump_x86_64.cpp @@ -116,7 +116,7 @@ lldb::DataBufferSP lldb_private::minidump::ConvertMinidumpContext_x86_64( writeRegister(&context->r15, result_base, reg_info[lldb_r15_x86_64]); } - // See comment on base regsiter + // See comment on base register if ((context_flags & LLDBSpecificFlag) == LLDBSpecificFlag) { writeBaseRegister(&context->fs_base, result_base, reg_info[x86_64_with_base::lldb_fs_base]); diff --git a/llvm/lib/Target/VE/VERegisterInfo.cpp b/llvm/lib/Target/VE/VERegisterInfo.cpp index 99e1f61c088eb..0c1183e2ac541 100644 --- a/llvm/lib/Target/VE/VERegisterInfo.cpp +++ b/llvm/lib/Target/VE/VERegisterInfo.cpp @@ -158,7 +158,7 @@ class EliminateFrameIndex { int64_t Bytes = 0); // Replace the frame index in \p MI with a frame register and a given offset // if it fits in the immediate field. Otherwise, use pre-calculated address - // in a clobber regsiter. + // in a clobber register. void replaceFI(MachineInstr &MI, Register FrameReg, int64_t Offset, int FIOperandNum); diff --git a/llvm/lib/Target/X86/X86RegisterInfo.td b/llvm/lib/Target/X86/X86RegisterInfo.td index bafea74f34403..63ad4b2bae5ac 100644 --- a/llvm/lib/Target/X86/X86RegisterInfo.td +++ b/llvm/lib/Target/X86/X86RegisterInfo.td @@ -83,7 +83,7 @@ def R15B : X86Reg<"r15b", 15>; // To achieve this, we do the following things: // 1. Set CostPerUse=1 for registers that need prefix // 2. Consider callee-save register is never cheaper than a register w/ cost 1 -// 3. List caller-save register before callee-save regsiter in RegisterClass +// 3. List caller-save register before callee-save register in RegisterClass // or AllocationOrder // // NOTE: diff --git a/llvm/test/CodeGen/AMDGPU/issue98474-need-live-out-undef-subregister-def.ll b/llvm/test/CodeGen/AMDGPU/issue98474-need-live-out-undef-subregister-def.ll index d226462ae156e..b0c3c990e3555 100644 --- a/llvm/test/CodeGen/AMDGPU/issue98474-need-live-out-undef-subregister-def.ll +++ b/llvm/test/CodeGen/AMDGPU/issue98474-need-live-out-undef-subregister-def.ll @@ -2,7 +2,7 @@ ; RUN: llc -mtriple=amdgpu9.00-amd-amdpal -o - %s | FileCheck %s ; Check for verifier error after tail duplication. An implicit_def of -; a subregsiter is needed to maintain liveness after assignment. +; a subregister is needed to maintain liveness after assignment. define amdgpu_vs void @test(i32 inreg %cmp, i32 %e0) { ; CHECK-LABEL: test: diff --git a/llvm/test/CodeGen/PowerPC/subreg-lanemasks.mir b/llvm/test/CodeGen/PowerPC/subreg-lanemasks.mir index cf69d3ad09878..c72939bb2a22c 100644 --- a/llvm/test/CodeGen/PowerPC/subreg-lanemasks.mir +++ b/llvm/test/CodeGen/PowerPC/subreg-lanemasks.mir @@ -3,7 +3,7 @@ # RUN: -debug-only=regalloc -o - %s 2>&1 | FileCheck %s # REQUIRES: asserts -# Keep track of all of the lanemasks for various subregsiters. +# Keep track of all of the lanemasks for various subregisters. # # CHECK: %3 [80r,80d:0) 0@80r L000000000000000C [80r,80d:0) 0@80r weight:0.000000e+00 # CHECK: %4 [96r,96d:0) 0@96r L0000000000003000 [96r,96d:0) 0@96r weight:0.000000e+00 diff --git a/llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-dfp-invalid.txt b/llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-dfp-invalid.txt index 5ea101cf9af39..a3ec5bb54e5a2 100644 --- a/llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-dfp-invalid.txt +++ b/llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-dfp-invalid.txt @@ -1,7 +1,7 @@ # RUN: llvm-mc --disassemble %s -mcpu=pwr10 -triple \ # RUN: powerpc64-unknown-linux-gnu < %s 2>&1 | FileCheck %s -# Regsiter for DSUBQ cannot be greater than 30. +# Register for DSUBQ cannot be greater than 30. # CHECK-NOT: dsubq 0, 6, 31 # CHECK: warning: invalid instruction encoding 0xfc 0x06 0xfc 0x04 diff --git a/llvm/test/TableGen/ArtificialRegs.td b/llvm/test/TableGen/ArtificialRegs.td index 2afce5a03db8f..8330aa9e9d7e5 100644 --- a/llvm/test/TableGen/ArtificialRegs.td +++ b/llvm/test/TableGen/ArtificialRegs.td @@ -25,7 +25,7 @@ def DA : RegisterClass<"D", [i64], 64, (add D0, A)>; // Make sure there are no DA_and_RA and DA_with_hi kind of // classes that only contain artificial registers or are inferred // copies of already existing register classes that only differ -// in the presence of artificial regsiters. +// in the presence of artificial registers. // // CHECK-LABEL: RegisterClass RA: // CHECK-NEXT: SpillSize: _______________________________________________ lldb-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
