================
@@ -813,9 +827,17 @@ def XSeqPairsClass : RegisterClass<"AArch64", [untyped],
64,
(add XSeqPairs)>{
let Size = 128;
}
+def SyspPairsClass : RegisterClass<"AArch64", [untyped], 64,
+ (add XSeqPairs, XZR_XZR)>{
+ let Size = 128;
+ // This is an asm/disasm operand class. XZR_XZR is used to model the SYSP
+ // Rt == 31 encoding and must not be allocated as a register pair.
+ let isAllocatable = 0;
----------------
jthackray wrote:
Ok, so removing `DUMMY_XZR` from `SyspPairsClass` allows this to be removed
now.
https://github.com/llvm/llvm-project/pull/182410
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