vsk updated this revision to Diff 372809.
vsk marked 3 inline comments as done.
vsk added a comment.
Address review feedback:
- Include far register in output, which now looks like e.g.:
(lldb) bt all
* thread #1, stop reason = ESR_EC_DABORT_EL0 (fault address:
0x6261747563657860)
* frame #0: 0x00000001aa5c2864 libsystem_platform.dylib`_platform_strlen + 4
- Include note that the exception class list can/does contain some
Apple-specific classes, but that it's largely 1:1 with the ARM spec.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D109795/new/
https://reviews.llvm.org/D109795
Files:
lldb/include/lldb/Target/AppleArm64ExceptionClass.def
lldb/include/lldb/Target/AppleArm64ExceptionClass.h
lldb/include/lldb/module.modulemap
lldb/source/Plugins/Process/mach-core/ThreadMachCore.cpp
Index: lldb/source/Plugins/Process/mach-core/ThreadMachCore.cpp
===================================================================
--- lldb/source/Plugins/Process/mach-core/ThreadMachCore.cpp
+++ lldb/source/Plugins/Process/mach-core/ThreadMachCore.cpp
@@ -9,7 +9,9 @@
#include "ThreadMachCore.h"
#include "lldb/Breakpoint/Watchpoint.h"
+#include "lldb/Host/SafeMachO.h"
#include "lldb/Symbol/ObjectFile.h"
+#include "lldb/Target/AppleArm64ExceptionClass.h"
#include "lldb/Target/Process.h"
#include "lldb/Target/RegisterContext.h"
#include "lldb/Target/StopInfo.h"
@@ -17,6 +19,7 @@
#include "lldb/Target/Unwind.h"
#include "lldb/Utility/ArchSpec.h"
#include "lldb/Utility/DataExtractor.h"
+#include "lldb/Utility/RegisterValue.h"
#include "lldb/Utility/State.h"
#include "lldb/Utility/StreamString.h"
@@ -91,7 +94,40 @@
bool ThreadMachCore::CalculateStopInfo() {
ProcessSP process_sp(GetProcess());
if (process_sp) {
- SetStopInfo(StopInfo::CreateStopReasonWithSignal(*this, SIGSTOP));
+ StopInfoSP stop_info;
+ RegisterContextSP reg_ctx_sp = GetRegisterContext();
+
+ if (reg_ctx_sp) {
+ Target &target = process_sp->GetTarget();
+ const ArchSpec arch_spec = target.GetArchitecture();
+ const uint32_t cputype = arch_spec.GetMachOCPUType();
+
+ if (cputype == llvm::MachO::CPU_TYPE_ARM64 ||
+ cputype == llvm::MachO::CPU_TYPE_ARM64_32) {
+ const RegisterInfo *esr_info = reg_ctx_sp->GetRegisterInfoByName("esr");
+ const RegisterInfo *far_info = reg_ctx_sp->GetRegisterInfoByName("far");
+ RegisterValue esr, far;
+ if (reg_ctx_sp->ReadRegister(esr_info, esr) &&
+ reg_ctx_sp->ReadRegister(far_info, far)) {
+ const uint32_t esr_val = esr.GetAsUInt32();
+ const AppleArm64ExceptionClass exception_class =
+ getAppleArm64ExceptionClass(esr_val);
+ if (exception_class !=
+ AppleArm64ExceptionClass::ESR_EC_UNCATEGORIZED) {
+ StreamString S;
+ S.Printf("%s (fault address: 0x%" PRIx64 ")",
+ toString(exception_class), far.GetAsUInt64());
+ stop_info =
+ StopInfo::CreateStopReasonWithException(*this, S.GetData());
+ }
+ }
+ }
+ }
+
+ if (!stop_info)
+ stop_info = StopInfo::CreateStopReasonWithSignal(*this, SIGSTOP);
+
+ SetStopInfo(stop_info);
return true;
}
return false;
Index: lldb/include/lldb/module.modulemap
===================================================================
--- lldb/include/lldb/module.modulemap
+++ lldb/include/lldb/module.modulemap
@@ -119,6 +119,7 @@
requires cplusplus
umbrella "Target"
+ textual header "Target/AppleArm64ExceptionClass.def"
module * { export * }
}
}
Index: lldb/include/lldb/Target/AppleArm64ExceptionClass.h
===================================================================
--- /dev/null
+++ lldb/include/lldb/Target/AppleArm64ExceptionClass.h
@@ -0,0 +1,48 @@
+//===-- AppleArm64ExceptionClass.h ------------------------------*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLDB_TARGET_APPLEARM64EXCEPTIONCLASS_H
+#define LLDB_TARGET_APPLEARM64EXCEPTIONCLASS_H
+
+namespace lldb_private {
+
+enum class AppleArm64ExceptionClass : unsigned {
+#define APPLE_ARM64_EXCEPTION_CLASS(Name, Code) Name = Code,
+#include "AppleArm64ExceptionClass.def"
+};
+
+/// Get the Apple ARM64 exception class encoded within \p esr.
+inline AppleArm64ExceptionClass getAppleArm64ExceptionClass(uint32_t esr) {
+ /*
+ * Exception Syndrome Register
+ *
+ * 31 26 25 24 0
+ * +------+--+------------------+
+ * | EC |IL| ISS |
+ * +------+--+------------------+
+ *
+ * EC - Exception Class
+ * IL - Instruction Length
+ * ISS - Instruction Specific Syndrome
+ */
+ return static_cast<AppleArm64ExceptionClass>(esr >> 26);
+}
+
+inline const char *toString(AppleArm64ExceptionClass EC) {
+ switch (EC) {
+#define APPLE_ARM64_EXCEPTION_CLASS(Name, Code) \
+ case AppleArm64ExceptionClass::Name: \
+ return #Name;
+#include "AppleArm64ExceptionClass.def"
+ }
+ return "Unknown Exception Class";
+}
+
+} // namespace lldb_private
+
+#endif // LLDB_TARGET_APPLEARM64EXCEPTIONCLASS_H
Index: lldb/include/lldb/Target/AppleArm64ExceptionClass.def
===================================================================
--- /dev/null
+++ lldb/include/lldb/Target/AppleArm64ExceptionClass.def
@@ -0,0 +1,50 @@
+/*===-- AppleArm64ExceptionClass.def ---------------------------*- C++ -*-=== *\
+|*
+|* Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+|* See https://llvm.org/LICENSE.txt for license information.
+|* SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+|*
+\*===----------------------------------------------------------------------===*/
+
+// Defines ESR exception classes for Apple arm64* targets.
+// These largely map 1:1 to the exception classes defined in ARM's architecture
+// reference manual, but there are some Apple-specific additions.
+
+#ifndef APPLE_ARM64_EXCEPTION_CLASS
+#error "APPLE_ARM64_EXCEPTION_CLASS(Name, Code) not defined."
+#endif
+
+APPLE_ARM64_EXCEPTION_CLASS(ESR_EC_UNCATEGORIZED, 0x00)
+APPLE_ARM64_EXCEPTION_CLASS(ESR_EC_WFI_WFE, 0x01)
+APPLE_ARM64_EXCEPTION_CLASS(ESR_EC_MCR_MRC_CP15_TRAP, 0x03)
+APPLE_ARM64_EXCEPTION_CLASS(ESR_EC_MCRR_MRRC_CP15_TRAP, 0x04)
+APPLE_ARM64_EXCEPTION_CLASS(ESR_EC_MCR_MRC_CP14_TRAP, 0x05)
+APPLE_ARM64_EXCEPTION_CLASS(ESR_EC_LDC_STC_CP14_TRAP, 0x06)
+APPLE_ARM64_EXCEPTION_CLASS(ESR_EC_TRAP_SIMD_FP, 0x07)
+APPLE_ARM64_EXCEPTION_CLASS(ESR_EC_PTRAUTH_INSTR_TRAP, 0x09)
+APPLE_ARM64_EXCEPTION_CLASS(ESR_EC_MCRR_MRRC_CP14_TRAP, 0x0c)
+APPLE_ARM64_EXCEPTION_CLASS(ESR_EC_ILLEGAL_INSTR_SET, 0x0e)
+APPLE_ARM64_EXCEPTION_CLASS(ESR_EC_SVC_32, 0x11)
+APPLE_ARM64_EXCEPTION_CLASS(ESR_EC_SVC_64, 0x15)
+APPLE_ARM64_EXCEPTION_CLASS(ESR_EC_MSR_TRAP, 0x18)
+APPLE_ARM64_EXCEPTION_CLASS(ESR_EC_PAC_FAIL, 0x1C)
+APPLE_ARM64_EXCEPTION_CLASS(ESR_EC_IABORT_EL0, 0x20)
+APPLE_ARM64_EXCEPTION_CLASS(ESR_EC_IABORT_EL1, 0x21)
+APPLE_ARM64_EXCEPTION_CLASS(ESR_EC_PC_ALIGN, 0x22)
+APPLE_ARM64_EXCEPTION_CLASS(ESR_EC_DABORT_EL0, 0x24)
+APPLE_ARM64_EXCEPTION_CLASS(ESR_EC_DABORT_EL1, 0x25)
+APPLE_ARM64_EXCEPTION_CLASS(ESR_EC_SP_ALIGN, 0x26)
+APPLE_ARM64_EXCEPTION_CLASS(ESR_EC_FLOATING_POINT_32, 0x28)
+APPLE_ARM64_EXCEPTION_CLASS(ESR_EC_FLOATING_POINT_64, 0x2C)
+APPLE_ARM64_EXCEPTION_CLASS(ESR_EC_SERROR_INTERRUPT, 0x2F)
+APPLE_ARM64_EXCEPTION_CLASS(ESR_EC_BKPT_REG_MATCH_EL0, 0x30)
+APPLE_ARM64_EXCEPTION_CLASS(ESR_EC_BKPT_REG_MATCH_EL1, 0x31)
+APPLE_ARM64_EXCEPTION_CLASS(ESR_EC_SW_STEP_DEBUG_EL0, 0x32)
+APPLE_ARM64_EXCEPTION_CLASS(ESR_EC_SW_STEP_DEBUG_EL1, 0x33)
+APPLE_ARM64_EXCEPTION_CLASS(ESR_EC_WATCHPT_MATCH_EL0, 0x34)
+APPLE_ARM64_EXCEPTION_CLASS(ESR_EC_WATCHPT_MATCH_EL1, 0x35)
+APPLE_ARM64_EXCEPTION_CLASS(ESR_EC_BKPT_AARCH32, 0x38)
+APPLE_ARM64_EXCEPTION_CLASS(ESR_EC_BRK_AARCH64, 0x3C)
+APPLE_ARM64_EXCEPTION_CLASS(ESR_EC_PRIV, 0x3F)
+
+#undef APPLE_ARM64_EXCEPTION_CLASS
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