[Lldb-commits] [PATCH] D131244: [LLDB] Missing break in a switch statement alters the execution flow.

[Slava Gurevich via Phabricator via lldb-commits]

fixathon created this revision.
fixathon added reviewers: clayborg, JDevlieghere, DavidSpickett.
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fixathon requested review of this revision.
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Looks like a typo from the past code changes.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D131244

Files:
  lldb/source/Plugins/Process/Utility/ARMUtils.h


Index: lldb/source/Plugins/Process/Utility/ARMUtils.h
===================================================================
--- lldb/source/Plugins/Process/Utility/ARMUtils.h
+++ lldb/source/Plugins/Process/Utility/ARMUtils.h
@@ -25,7 +25,8 @@
                                       ARM_ShifterType &shift_t) {
   switch (type) {
   default:
-  // assert(0 && "Invalid shift type");
+    // assert(0 && "Invalid shift type");
+    break;
   case 0:
     shift_t = SRType_LSL;
     return imm5;
@@ -311,6 +312,8 @@
   if (bits(imm12, 11, 10) == 0) {
     switch (bits(imm12, 9, 8)) {
     default: // Keep static analyzer happy with a default case
+      break;
+
     case 0:
       imm32 = abcdefgh;
       break;



Index: lldb/source/Plugins/Process/Utility/ARMUtils.h
===================================================================
--- lldb/source/Plugins/Process/Utility/ARMUtils.h
+++ lldb/source/Plugins/Process/Utility/ARMUtils.h
@@ -25,7 +25,8 @@
                                       ARM_ShifterType &shift_t) {
   switch (type) {
   default:
-  // assert(0 && "Invalid shift type");
+    // assert(0 && "Invalid shift type");
+    break;
   case 0:
     shift_t = SRType_LSL;
     return imm5;
@@ -311,6 +312,8 @@
   if (bits(imm12, 11, 10) == 0) {
     switch (bits(imm12, 9, 8)) {
     default: // Keep static analyzer happy with a default case
+      break;
+
     case 0:
       imm32 = abcdefgh;
       break;

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