DavidSpickett added a comment.
> I suspect that it may be the case that for example, writing to the bottom 128
> bits of streaming mode z0 may not be reflected in the SIMD unit's v0. Or at
> least, one could build a core that acted that way.
But the user would be very confused by this given that if you are stopped here
in streaming mode:
mov v0.d[0] x0
That instruction would actually see the bottom 128 bits of streaming z0, even
if elsewhere there is another, inactive v0 register in the core. If the user
then does `register write v0 {....}` I doubt they would expect it to mode
switch and write to a whole different v0, it should update z0.
So even if on a hardware level this configuration is possible, I don't think
it's good to have the debugger act this way. Better that we think of this from
the perspective of a running instruction, what would it see and therefore what
would the user expect to happen.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D155269/new/
https://reviews.llvm.org/D155269
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