DavidSpickett added inline comments.
================
Comment at:
lldb/test/API/commands/register/register/aarch64_dynamic_regset/TestArm64DynamicRegsets.py:201
+ self.runCmd("register write za '{}'".format(za_value))
+ self.expect("register read za", substrs=[za_value])
----------------
omjavaid wrote:
> How can we differentiate between disabled ZA (read as all zeros) and enabled
> ZA actually set to all zeros?
In this specific test we write a non-zero value to avoid that issue, but I
assume you mean generally.
The user should refer to the SVCR register, SVCR.ZA specifically, to know if
the value they're seeing is the active ZA or not. You can see an example of
that if you look at the changes to this file in
https://reviews.llvm.org/D154927.
Again, the user has to know what bit to look for but I'll eventually address
that with the register fields work.
================
Comment at:
lldb/test/API/commands/register/register/aarch64_za_register/za_dynamic_resize/Makefile:3
+
+CFLAGS_EXTRAS := -march=armv8-a+sve+sme -lpthread
+
----------------
omjavaid wrote:
> is USE_SSVE a subset of sve+sme?
It's a define I made up for the purposes of the test, it's in the existing
tests but not well documented. I'll push something to address that in the
existing tests and check the new ones here for this and other defines I've
added.
We need sve to update sve registers and sme to be able to move into the za
register (/the rows of the za register).
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D159505/new/
https://reviews.llvm.org/D159505
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