================
@@ -115,8 +148,23 @@ Status
NativeProcessSoftwareSingleStep::SetupSoftwareSingleStepping(
emulator_up->SetWriteMemCallback(&WriteMemoryCallback);
emulator_up->SetWriteRegCallback(&WriteRegisterCallback);
- if (!emulator_up->ReadInstruction())
- return Status("Read instruction failed!");
+ if (!emulator_up->ReadInstruction()) {
+ // try to get at least the size of next instruction to set breakpoint.
+ auto instrSizeOpt = emulator_up->GetLastInstrSize();
+ if (!instrSizeOpt)
+ return Status("Read instruction failed!");
+ bool success = false;
+ auto pc = emulator_up->ReadRegisterUnsigned(eRegisterKindGeneric,
+ LLDB_REGNUM_GENERIC_PC,
+ LLDB_INVALID_ADDRESS,
&success);
+ if (!success)
+ return Status("Reading pc failed!");
+ lldb::addr_t next_pc = pc + *instrSizeOpt;
+ auto Result =
+ SetSoftwareBreakPointOnPC(arch, next_pc, /* next_flags */ 0x0,
process);
----------------
jasonmolenda wrote:
We've decoded the length of the instruction at `pc` at this point, and them to
get `next_pc`. Then we pass `next_pc` to this method which has a hardcoded
size of 4 for RISCV. It's only a hint that is sent to lldb-server as it tries
to step over the instruction. With armv7/aarch32 we had to get arm/thumb
breakpoint instructions correct because an arm breakpoint wasn't valid when the
processor was in thumb mode (iirc) but RISC-V doesn't have a processor mode
like that iiuc. So maybe it's fine to have `SetSoftwareBreakPointOnPC`
hardcoding 4 for the next RISCV breakpoint.
https://github.com/llvm/llvm-project/pull/90075
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