Hi all!
This is a quick update on some work I have been doing on the linux
front, specifically a Process plugin for that platform.
The current effort is still at an early stage. In short, we can launch
an inferior process and set/step-over breakpoints.
However, I am thinking about merging this initial work into the tree
sooner rather than later to avoid dumping a huge patch on everyone at a
later time. Although *not quite ready*, you can see the current plugin
code here:
http://github.com/ice799/lldb/tree/swilson-process/source/Plugins/Process/Linux
A few issues I came across while working on this which should be
resolved before the linux plugin can be merged:
- We need to make the dwarf debug section names (as defined
SymbolFileDwarf.cpp) selectable by platform. I implemented a simple
macro hack to work around this for now. A better solution might be
to have a header #define the section names. Any suggestions
appreciated:
http://github.com/ice799/lldb/commit/284c444cae1feedc39f48ffed1265abf3fea291c
- There is a good bit of sharable code in the MacOSX-User plugin with
respect to RegisterContext specializations. Please find attached two
files which provide a partial x86_64 RegisterContext specialization.
The idea is to introduce
lldb/include/Target/X86/RegisterContext_x86_64.h so all all plugins
can share common definitions and code. Again, any thoughts or
suggestions on this approach appreciated!
Take care,
Steve
//===-- RegisterContext_x86_64.cpp ------------------------------*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
#ifndef liblldb_RegisterContext_x86_64_H_
#define liblldb_RegisterContext_x86_64_H_
#include "lldb/Target/RegisterContext.h"
namespace lldb_private {
//------------------------------------------------------------------------------
/// @class RegisterContext_x86_64
/// @brief Parital specialization for x86_64 RegisterContext implementations.
///
/// This class provides generic register number definitions and RegisterSet
/// entries for the x86_64 platform. Specific platform plugins can further
/// refine this class to provide complete support for their respective platform.
class RegisterContext_x86_64
: public lldb_private::RegisterContext
{
public:
RegisterContext_x86_64(lldb_private::Thread &thread,
lldb_private::StackFrame *frame);
/// Converts a generic LLDB register kind and number to the corresponding
/// X86_64RegNum value, or LLDB_INVALID_REGNUM if there is no
/// correspondence.
uint32_t
ConvertRegisterKindToRegisterNumber(uint32_t kind, uint32_t num);
protected:
/// The generic implementation provides definitions for the GPR and FPU
/// register sets (the latter includes MMX and XMM registers). The
/// following constant defines the number of default sets supported. If a
/// subclass wishes to provided additional register sets it may allocate
/// indices above this value.
enum {
k_num_generic_register_sets = 2
};
public:
/// Returns the total number of registers contained in the default register
/// sets. May be extended by subclasses.
virtual size_t
GetRegisterCount();
/// Default implementation returns k_num_generic_register_sets. May be
/// extended by subclasses.
virtual size_t
GetRegisterSetCount();
/// Returns a generic register set. May be extended by subclasses.
virtual const lldb::RegisterSet *
GetRegisterSet(uint32_t set);
//------------------------------------------------------------------
// x86_64 register names.
//------------------------------------------------------------------
enum X86_64RegNumber
{
gpr_rax = 0,
gpr_rbx,
gpr_rcx,
gpr_rdx,
gpr_rdi,
gpr_rsi,
gpr_rbp,
gpr_rsp,
gpr_r8,
gpr_r9,
gpr_r10,
gpr_r11,
gpr_r12,
gpr_r13,
gpr_r14,
gpr_r15,
gpr_rip,
gpr_rflags,
gpr_cs,
gpr_fs,
gpr_gs,
k_num_gpr_registers,
fpu_fcw = k_num_gpr_registers,
fpu_fsw,
fpu_ftw,
fpu_fop,
fpu_ip,
fpu_cs,
fpu_dp,
fpu_ds,
fpu_mxcsr,
fpu_mxcsrmask,
fpu_stmm0,
fpu_stmm1,
fpu_stmm2,
fpu_stmm3,
fpu_stmm4,
fpu_stmm5,
fpu_stmm6,
fpu_stmm7,
fpu_xmm0,
fpu_xmm1,
fpu_xmm2,
fpu_xmm3,
fpu_xmm4,
fpu_xmm5,
fpu_xmm6,
fpu_xmm7,
fpu_xmm8,
fpu_xmm9,
fpu_xmm10,
fpu_xmm11,
fpu_xmm12,
fpu_xmm13,
fpu_xmm14,
fpu_xmm15,
k_num_registers,
k_num_fpu_registers = k_num_registers - k_num_gpr_registers,
// Aliases
fpu_fctrl = fpu_fcw,
fpu_fstat = fpu_fsw,
fpu_ftag = fpu_ftw,
fpu_fiseg = fpu_cs,
fpu_fioff = fpu_ip,
fpu_foseg = fpu_ds,
fpu_fooff = fpu_dp
};
//------------------------------------------------------------------
// GDB register names.
//------------------------------------------------------------------
enum gdb_regnums
{
gdb_gpr_rax = 0,
gdb_gpr_rbx = 1,
gdb_gpr_rcx = 2,
gdb_gpr_rdx = 3,
gdb_gpr_rsi = 4,
gdb_gpr_rdi = 5,
gdb_gpr_rbp = 6,
gdb_gpr_rsp = 7,
gdb_gpr_r8 = 8,
gdb_gpr_r9 = 9,
gdb_gpr_r10 = 10,
gdb_gpr_r11 = 11,
gdb_gpr_r12 = 12,
gdb_gpr_r13 = 13,
gdb_gpr_r14 = 14,
gdb_gpr_r15 = 15,
gdb_gpr_rip = 16,
gdb_gpr_rflags = 17,
gdb_gpr_cs = 18,
gdb_gpr_ss = 19,
gdb_gpr_ds = 20,
gdb_gpr_es = 21,
gdb_gpr_fs = 22,
gdb_gpr_gs = 23,
gdb_fpu_stmm0 = 24,
gdb_fpu_stmm1 = 25,
gdb_fpu_stmm2 = 26,
gdb_fpu_stmm3 = 27,
gdb_fpu_stmm4 = 28,
gdb_fpu_stmm5 = 29,
gdb_fpu_stmm6 = 30,
gdb_fpu_stmm7 = 31,
gdb_fpu_fctrl = 32, gdb_fpu_fcw = gdb_fpu_fctrl,
gdb_fpu_fstat = 33, gdb_fpu_fsw = gdb_fpu_fstat,
gdb_fpu_ftag = 34, gdb_fpu_ftw = gdb_fpu_ftag,
gdb_fpu_fiseg = 35, gdb_fpu_cs = gdb_fpu_fiseg,
gdb_fpu_fioff = 36, gdb_fpu_ip = gdb_fpu_fioff,
gdb_fpu_foseg = 37, gdb_fpu_ds = gdb_fpu_foseg,
gdb_fpu_fooff = 38, gdb_fpu_dp = gdb_fpu_fooff,
gdb_fpu_fop = 39,
gdb_fpu_xmm0 = 40,
gdb_fpu_xmm1 = 41,
gdb_fpu_xmm2 = 42,
gdb_fpu_xmm3 = 43,
gdb_fpu_xmm4 = 44,
gdb_fpu_xmm5 = 45,
gdb_fpu_xmm6 = 46,
gdb_fpu_xmm7 = 47,
gdb_fpu_xmm8 = 48,
gdb_fpu_xmm9 = 49,
gdb_fpu_xmm10 = 50,
gdb_fpu_xmm11 = 51,
gdb_fpu_xmm12 = 52,
gdb_fpu_xmm13 = 53,
gdb_fpu_xmm14 = 54,
gdb_fpu_xmm15 = 55,
gdb_fpu_mxcsr = 56
};
//------------------------------------------------------------------
// GCC DWARF register names.
//------------------------------------------------------------------
enum gcc_dwarf_regnums
{
gcc_dwarf_gpr_rax = 0,
gcc_dwarf_gpr_rdx,
gcc_dwarf_gpr_rcx,
gcc_dwarf_gpr_rbx,
gcc_dwarf_gpr_rsi,
gcc_dwarf_gpr_rdi,
gcc_dwarf_gpr_rbp,
gcc_dwarf_gpr_rsp,
gcc_dwarf_gpr_r8,
gcc_dwarf_gpr_r9,
gcc_dwarf_gpr_r10,
gcc_dwarf_gpr_r11,
gcc_dwarf_gpr_r12,
gcc_dwarf_gpr_r13,
gcc_dwarf_gpr_r14,
gcc_dwarf_gpr_r15,
gcc_dwarf_gpr_rip,
gcc_dwarf_fpu_xmm0,
gcc_dwarf_fpu_xmm1,
gcc_dwarf_fpu_xmm2,
gcc_dwarf_fpu_xmm3,
gcc_dwarf_fpu_xmm4,
gcc_dwarf_fpu_xmm5,
gcc_dwarf_fpu_xmm6,
gcc_dwarf_fpu_xmm7,
gcc_dwarf_fpu_xmm8,
gcc_dwarf_fpu_xmm9,
gcc_dwarf_fpu_xmm10,
gcc_dwarf_fpu_xmm11,
gcc_dwarf_fpu_xmm12,
gcc_dwarf_fpu_xmm13,
gcc_dwarf_fpu_xmm14,
gcc_dwarf_fpu_xmm15,
gcc_dwarf_fpu_stmm0,
gcc_dwarf_fpu_stmm1,
gcc_dwarf_fpu_stmm2,
gcc_dwarf_fpu_stmm3,
gcc_dwarf_fpu_stmm4,
gcc_dwarf_fpu_stmm5,
gcc_dwarf_fpu_stmm6,
gcc_dwarf_fpu_stmm7
};
protected:
static const lldb::RegisterSet g_reg_sets[k_num_generic_register_sets];
static const uint32_t g_gpr_regnums[k_num_gpr_registers];
static const uint32_t g_fpu_regnums[k_num_fpu_registers];
};
} // End lldb_private namesapce.
#endif // #ifndef liblldb_RegisterContext_x86_64_H_
//===-- RegisterContext_x86_64.cpp ------------------------------*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
#include "lldb/Target/X86/RegisterContext_x86_64.h"
using namespace lldb_private;
RegisterContext_x86_64::RegisterContext_x86_64(Thread &thread,
StackFrame *frame)
: RegisterContext(thread, frame)
{
}
uint32_t
RegisterContext_x86_64::ConvertRegisterKindToRegisterNumber(uint32_t kind,
uint32_t num)
{
if (kind == lldb::eRegisterKindGeneric)
{
switch (num)
{
case LLDB_REGNUM_GENERIC_PC: return gpr_rip;
case LLDB_REGNUM_GENERIC_SP: return gpr_rsp;
case LLDB_REGNUM_GENERIC_FP: return gpr_rbp;
case LLDB_REGNUM_GENERIC_FLAGS: return gpr_rflags;
case LLDB_REGNUM_GENERIC_RA:
default:
return LLDB_INVALID_REGNUM;
}
}
if (kind == lldb::eRegisterKindGCC || kind == lldb::eRegisterKindDWARF)
{
switch (num)
{
case gcc_dwarf_gpr_rax: return gpr_rax;
case gcc_dwarf_gpr_rdx: return gpr_rdx;
case gcc_dwarf_gpr_rcx: return gpr_rcx;
case gcc_dwarf_gpr_rbx: return gpr_rbx;
case gcc_dwarf_gpr_rsi: return gpr_rsi;
case gcc_dwarf_gpr_rdi: return gpr_rdi;
case gcc_dwarf_gpr_rbp: return gpr_rbp;
case gcc_dwarf_gpr_rsp: return gpr_rsp;
case gcc_dwarf_gpr_r8: return gpr_r8;
case gcc_dwarf_gpr_r9: return gpr_r9;
case gcc_dwarf_gpr_r10: return gpr_r10;
case gcc_dwarf_gpr_r11: return gpr_r11;
case gcc_dwarf_gpr_r12: return gpr_r12;
case gcc_dwarf_gpr_r13: return gpr_r13;
case gcc_dwarf_gpr_r14: return gpr_r14;
case gcc_dwarf_gpr_r15: return gpr_r15;
case gcc_dwarf_gpr_rip: return gpr_rip;
case gcc_dwarf_fpu_xmm0: return fpu_xmm0;
case gcc_dwarf_fpu_xmm1: return fpu_xmm1;
case gcc_dwarf_fpu_xmm2: return fpu_xmm2;
case gcc_dwarf_fpu_xmm3: return fpu_xmm3;
case gcc_dwarf_fpu_xmm4: return fpu_xmm4;
case gcc_dwarf_fpu_xmm5: return fpu_xmm5;
case gcc_dwarf_fpu_xmm6: return fpu_xmm6;
case gcc_dwarf_fpu_xmm7: return fpu_xmm7;
case gcc_dwarf_fpu_xmm8: return fpu_xmm8;
case gcc_dwarf_fpu_xmm9: return fpu_xmm9;
case gcc_dwarf_fpu_xmm10: return fpu_xmm10;
case gcc_dwarf_fpu_xmm11: return fpu_xmm11;
case gcc_dwarf_fpu_xmm12: return fpu_xmm12;
case gcc_dwarf_fpu_xmm13: return fpu_xmm13;
case gcc_dwarf_fpu_xmm14: return fpu_xmm14;
case gcc_dwarf_fpu_xmm15: return fpu_xmm15;
case gcc_dwarf_fpu_stmm0: return fpu_stmm0;
case gcc_dwarf_fpu_stmm1: return fpu_stmm1;
case gcc_dwarf_fpu_stmm2: return fpu_stmm2;
case gcc_dwarf_fpu_stmm3: return fpu_stmm3;
case gcc_dwarf_fpu_stmm4: return fpu_stmm4;
case gcc_dwarf_fpu_stmm5: return fpu_stmm5;
case gcc_dwarf_fpu_stmm6: return fpu_stmm6;
case gcc_dwarf_fpu_stmm7: return fpu_stmm7;
default:
return LLDB_INVALID_REGNUM;
}
}
if (kind == lldb::eRegisterKindGDB)
{
switch (num)
{
case gdb_gpr_rax : return gpr_rax;
case gdb_gpr_rbx : return gpr_rbx;
case gdb_gpr_rcx : return gpr_rcx;
case gdb_gpr_rdx : return gpr_rdx;
case gdb_gpr_rsi : return gpr_rsi;
case gdb_gpr_rdi : return gpr_rdi;
case gdb_gpr_rbp : return gpr_rbp;
case gdb_gpr_rsp : return gpr_rsp;
case gdb_gpr_r8 : return gpr_r8;
case gdb_gpr_r9 : return gpr_r9;
case gdb_gpr_r10 : return gpr_r10;
case gdb_gpr_r11 : return gpr_r11;
case gdb_gpr_r12 : return gpr_r12;
case gdb_gpr_r13 : return gpr_r13;
case gdb_gpr_r14 : return gpr_r14;
case gdb_gpr_r15 : return gpr_r15;
case gdb_gpr_rip : return gpr_rip;
case gdb_gpr_rflags : return gpr_rflags;
case gdb_gpr_cs : return gpr_cs;
// FIXME: Just copy what is in "gs" for "ss", "ds" and "es" (for now).
case gdb_gpr_ss : return gpr_gs;
case gdb_gpr_ds : return gpr_gs;
case gdb_gpr_es : return gpr_gs;
case gdb_gpr_fs : return gpr_fs;
case gdb_gpr_gs : return gpr_gs;
case gdb_fpu_stmm0 : return fpu_stmm0;
case gdb_fpu_stmm1 : return fpu_stmm1;
case gdb_fpu_stmm2 : return fpu_stmm2;
case gdb_fpu_stmm3 : return fpu_stmm3;
case gdb_fpu_stmm4 : return fpu_stmm4;
case gdb_fpu_stmm5 : return fpu_stmm5;
case gdb_fpu_stmm6 : return fpu_stmm6;
case gdb_fpu_stmm7 : return fpu_stmm7;
case gdb_fpu_fctrl : return fpu_fctrl;
case gdb_fpu_fstat : return fpu_fstat;
case gdb_fpu_ftag : return fpu_ftag;
case gdb_fpu_fiseg : return fpu_fiseg;
case gdb_fpu_fioff : return fpu_fioff;
case gdb_fpu_foseg : return fpu_foseg;
case gdb_fpu_fooff : return fpu_fooff;
case gdb_fpu_fop : return fpu_fop;
case gdb_fpu_xmm0 : return fpu_xmm0;
case gdb_fpu_xmm1 : return fpu_xmm1;
case gdb_fpu_xmm2 : return fpu_xmm2;
case gdb_fpu_xmm3 : return fpu_xmm3;
case gdb_fpu_xmm4 : return fpu_xmm4;
case gdb_fpu_xmm5 : return fpu_xmm5;
case gdb_fpu_xmm6 : return fpu_xmm6;
case gdb_fpu_xmm7 : return fpu_xmm7;
case gdb_fpu_xmm8 : return fpu_xmm8;
case gdb_fpu_xmm9 : return fpu_xmm9;
case gdb_fpu_xmm10 : return fpu_xmm10;
case gdb_fpu_xmm11 : return fpu_xmm11;
case gdb_fpu_xmm12 : return fpu_xmm12;
case gdb_fpu_xmm13 : return fpu_xmm13;
case gdb_fpu_xmm14 : return fpu_xmm14;
case gdb_fpu_xmm15 : return fpu_xmm15;
case gdb_fpu_mxcsr : return fpu_mxcsr;
default:
return LLDB_INVALID_REGNUM;
}
}
return LLDB_INVALID_REGNUM;
}
size_t
RegisterContext_x86_64::GetRegisterCount()
{
return k_num_registers;
}
size_t
RegisterContext_x86_64::GetRegisterSetCount()
{
return k_num_generic_register_sets;
}
const lldb::RegisterSet *
RegisterContext_x86_64::GetRegisterSet(uint32_t set)
{
if (set < k_num_generic_register_sets)
return &g_reg_sets[set];
return NULL;
}
//------------------------------------------------------------------------------
// Static RegisterSet data.
const lldb::RegisterSet
RegisterContext_x86_64::g_reg_sets[k_num_generic_register_sets] =
{
{ "General Purpose Registers", "gpr", k_num_gpr_registers, g_gpr_regnums },
{ "Floating Point Registers", "fpu", k_num_fpu_registers, g_fpu_regnums }
};
const uint32_t
RegisterContext_x86_64::g_gpr_regnums[k_num_gpr_registers] =
{
gpr_rax,
gpr_rbx,
gpr_rcx,
gpr_rdx,
gpr_rdi,
gpr_rsi,
gpr_rbp,
gpr_rsp,
gpr_r8,
gpr_r9,
gpr_r10,
gpr_r11,
gpr_r12,
gpr_r13,
gpr_r14,
gpr_r15,
gpr_rip,
gpr_rflags,
gpr_cs,
gpr_fs,
gpr_gs
};
const uint32_t
RegisterContext_x86_64::g_fpu_regnums[k_num_fpu_registers] =
{
fpu_fcw,
fpu_fsw,
fpu_ftw,
fpu_fop,
fpu_ip,
fpu_cs,
fpu_dp,
fpu_ds,
fpu_mxcsr,
fpu_mxcsrmask,
fpu_stmm0,
fpu_stmm1,
fpu_stmm2,
fpu_stmm3,
fpu_stmm4,
fpu_stmm5,
fpu_stmm6,
fpu_stmm7,
fpu_xmm0,
fpu_xmm1,
fpu_xmm2,
fpu_xmm3,
fpu_xmm4,
fpu_xmm5,
fpu_xmm6,
fpu_xmm7,
fpu_xmm8,
fpu_xmm9,
fpu_xmm10,
fpu_xmm11,
fpu_xmm12,
fpu_xmm13,
fpu_xmm14,
fpu_xmm15
};
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