Ed,
Attached is patch for basic, get-it-going, support for freebsd arm to lldb.
lldb was cross built on 10.1 amd64 with llvm ToT.
Run on 10.1 arm/pandaboard.
Tom
>From 36465729a66b0fc13228a102e6855289a73afe5b Mon Sep 17 00:00:00 2001
From: Tom <t...@bumblecow.com>
Date: Mon, 13 Apr 2015 02:25:52 -0500
Subject: [PATCH] Add support for FreeBSD arm
Create class file for RegisterContextFreeBSD_arm
Define the general registers in the register interface
Add RegisterContextFreeBSD_arm.cpp to CMakeLists.txt to add to cmake build
Use the RegisterContextFreeBSD_arm in POSIXThread::GetRegisterContext
This hooks up the freebsd arm register interface to posix thread.
Fix RegisterContextPOSIX_arm::GetRegisterSet
The target triple should be 'arm' not 'aarch64'
Add arm sw brkpt insn to PlatformFreeBSD::GetSoftwareBreakpointTrapOpcode
---
.../Plugins/Platform/FreeBSD/PlatformFreeBSD.cpp | 6 +
source/Plugins/Process/POSIX/POSIXThread.cpp | 7 +-
source/Plugins/Process/Utility/CMakeLists.txt | 1 +
.../Process/Utility/RegisterContextFreeBSD_arm.cpp | 240 +++++++++++++++++++++
.../Process/Utility/RegisterContextFreeBSD_arm.h | 27 +++
.../Process/Utility/RegisterContextPOSIX_arm.cpp | 2 +-
6 files changed, 281 insertions(+), 2 deletions(-)
create mode 100644 source/Plugins/Process/Utility/RegisterContextFreeBSD_arm.cpp
create mode 100644 source/Plugins/Process/Utility/RegisterContextFreeBSD_arm.h
diff --git a/source/Plugins/Platform/FreeBSD/PlatformFreeBSD.cpp b/source/Plugins/Platform/FreeBSD/PlatformFreeBSD.cpp
index dd2ecfc..32b4bd3 100644
--- a/source/Plugins/Platform/FreeBSD/PlatformFreeBSD.cpp
+++ b/source/Plugins/Platform/FreeBSD/PlatformFreeBSD.cpp
@@ -344,6 +344,12 @@ PlatformFreeBSD::GetSoftwareBreakpointTrapOpcode (Target &target, BreakpointSite
trap_opcode = g_ppc_opcode;
trap_opcode_size = sizeof(g_ppc_opcode);
}
+ case llvm::Triple::arm:
+ {
+ static const uint8_t g_arm_opcode[] = { 0xfe, 0xde, 0xff, 0xe7 };
+ trap_opcode = g_arm_opcode;
+ trap_opcode_size = sizeof(g_arm_opcode);
+ }
}
if (bp_site->SetTrapOpcode(trap_opcode, trap_opcode_size))
diff --git a/source/Plugins/Process/POSIX/POSIXThread.cpp b/source/Plugins/Process/POSIX/POSIXThread.cpp
index 6ae6683..931a2e4 100644
--- a/source/Plugins/Process/POSIX/POSIXThread.cpp
+++ b/source/Plugins/Process/POSIX/POSIXThread.cpp
@@ -41,6 +41,7 @@
#include "Plugins/Process/Utility/RegisterContextLinux_arm64.h"
#include "Plugins/Process/Utility/RegisterContextLinux_i386.h"
#include "Plugins/Process/Utility/RegisterContextLinux_x86_64.h"
+#include "Plugins/Process/Utility/RegisterContextFreeBSD_arm.h"
#include "Plugins/Process/Utility/RegisterContextFreeBSD_i386.h"
#include "Plugins/Process/Utility/RegisterContextFreeBSD_mips64.h"
#include "Plugins/Process/Utility/RegisterContextFreeBSD_powerpc.h"
@@ -171,7 +172,11 @@ POSIXThread::GetRegisterContext()
case llvm::Triple::FreeBSD:
switch (target_arch.GetMachine())
{
- case llvm::Triple::ppc:
+ case llvm::Triple::arm:
+ reg_interface = new RegisterContextFreeBSD_arm(target_arch);
+ break;
+
+ case llvm::Triple::ppc:
#ifndef __powerpc64__
reg_interface = new RegisterContextFreeBSD_powerpc32(target_arch);
break;
diff --git a/source/Plugins/Process/Utility/CMakeLists.txt b/source/Plugins/Process/Utility/CMakeLists.txt
index 00ed362..0b0b6ac 100644
--- a/source/Plugins/Process/Utility/CMakeLists.txt
+++ b/source/Plugins/Process/Utility/CMakeLists.txt
@@ -15,6 +15,7 @@ add_lldb_library(lldbPluginProcessUtility
RegisterContextDarwin_i386.cpp
RegisterContextDarwin_x86_64.cpp
RegisterContextDummy.cpp
+ RegisterContextFreeBSD_arm.cpp
RegisterContextFreeBSD_arm64.cpp
RegisterContextFreeBSD_i386.cpp
RegisterContextFreeBSD_mips64.cpp
diff --git a/source/Plugins/Process/Utility/RegisterContextFreeBSD_arm.cpp b/source/Plugins/Process/Utility/RegisterContextFreeBSD_arm.cpp
new file mode 100644
index 0000000..af8697f
--- /dev/null
+++ b/source/Plugins/Process/Utility/RegisterContextFreeBSD_arm.cpp
@@ -0,0 +1,240 @@
+//===-- RegisterContextFreeBSD_arm.cpp ------------------------*- C++ -*-===//
+//
+// The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===---------------------------------------------------------------------===//
+
+#include "RegisterContextFreeBSD_arm.h"
+
+using namespace lldb_private;
+using namespace lldb;
+
+// http://svnweb.freebsd.org/base/head/sys/arm/include/reg.h
+struct reg
+{
+ uint32_t r[13];
+ uint32_t r_sp;
+ uint32_t r_lr;
+ uint32_t r_pc;
+ uint32_t r_cpsr;
+};
+
+RegisterContextFreeBSD_arm::RegisterContextFreeBSD_arm(const ArchSpec &target_arch)
+ : RegisterInfoInterface(target_arch)
+{
+}
+
+size_t
+RegisterContextFreeBSD_arm::GetGPRSize() const
+{
+ return sizeof(reg);
+}
+
+#include "ARM_GCC_Registers.h"
+#include "ARM_DWARF_Registers.h"
+
+enum
+{
+ gpr_r0 = 0,
+ gpr_r1,
+ gpr_r2,
+ gpr_r3,
+ gpr_r4,
+ gpr_r5,
+ gpr_r6,
+ gpr_r7,
+ gpr_r8,
+ gpr_r9,
+ gpr_r10,
+ gpr_r11,
+ gpr_r12,
+ gpr_r13,
+ gpr_sp = gpr_r13,
+ gpr_r14,
+ gpr_lr = gpr_r14,
+ gpr_r15,
+ gpr_pc = gpr_r15,
+ gpr_cpsr,
+
+ k_num_registers
+};
+
+#define GPR_OFFSET(idx) ((idx)*4)
+static RegisterInfo g_register_infos_arm[] = {
+ // name, alt_name, byte_size, byte_offset, encoding, format, kinds, value_regs, invalidate_regs
+ {"r0",
+ NULL,
+ 4,
+ GPR_OFFSET(0),
+ eEncodingUint,
+ eFormatHex,
+ {gcc_r0, dwarf_r0, LLDB_INVALID_REGNUM, gdb_arm_r0, gpr_r0},
+ NULL,
+ NULL},
+ {"r1",
+ NULL,
+ 4,
+ GPR_OFFSET(1),
+ eEncodingUint,
+ eFormatHex,
+ {gcc_r1, dwarf_r1, LLDB_INVALID_REGNUM, gdb_arm_r1, gpr_r1},
+ NULL,
+ NULL},
+ {"r2",
+ NULL,
+ 4,
+ GPR_OFFSET(2),
+ eEncodingUint,
+ eFormatHex,
+ {gcc_r2, dwarf_r2, LLDB_INVALID_REGNUM, gdb_arm_r2, gpr_r2},
+ NULL,
+ NULL},
+ {"r3",
+ NULL,
+ 4,
+ GPR_OFFSET(3),
+ eEncodingUint,
+ eFormatHex,
+ {gcc_r3, dwarf_r3, LLDB_INVALID_REGNUM, gdb_arm_r3, gpr_r3},
+ NULL,
+ NULL},
+ {"r4",
+ NULL,
+ 4,
+ GPR_OFFSET(4),
+ eEncodingUint,
+ eFormatHex,
+ {gcc_r4, dwarf_r4, LLDB_INVALID_REGNUM, gdb_arm_r4, gpr_r4},
+ NULL,
+ NULL},
+ {"r5",
+ NULL,
+ 4,
+ GPR_OFFSET(5),
+ eEncodingUint,
+ eFormatHex,
+ {gcc_r5, dwarf_r5, LLDB_INVALID_REGNUM, gdb_arm_r5, gpr_r5},
+ NULL,
+ NULL},
+ {"r6",
+ NULL,
+ 4,
+ GPR_OFFSET(6),
+ eEncodingUint,
+ eFormatHex,
+ {gcc_r6, dwarf_r6, LLDB_INVALID_REGNUM, gdb_arm_r6, gpr_r6},
+ NULL,
+ NULL},
+ {"r7",
+ NULL,
+ 4,
+ GPR_OFFSET(7),
+ eEncodingUint,
+ eFormatHex,
+ {gcc_r7, dwarf_r7, LLDB_REGNUM_GENERIC_FP, gdb_arm_r7, gpr_r7},
+ NULL,
+ NULL},
+ {"r8",
+ NULL,
+ 4,
+ GPR_OFFSET(8),
+ eEncodingUint,
+ eFormatHex,
+ {gcc_r8, dwarf_r8, LLDB_INVALID_REGNUM, gdb_arm_r8, gpr_r8},
+ NULL,
+ NULL},
+ {"r9",
+ NULL,
+ 4,
+ GPR_OFFSET(9),
+ eEncodingUint,
+ eFormatHex,
+ {gcc_r9, dwarf_r9, LLDB_INVALID_REGNUM, gdb_arm_r9, gpr_r9},
+ NULL,
+ NULL},
+ {"r10",
+ NULL,
+ 4,
+ GPR_OFFSET(10),
+ eEncodingUint,
+ eFormatHex,
+ {gcc_r10, dwarf_r10, LLDB_INVALID_REGNUM, gdb_arm_r10, gpr_r10},
+ NULL,
+ NULL},
+ {"r11",
+ NULL,
+ 4,
+ GPR_OFFSET(11),
+ eEncodingUint,
+ eFormatHex,
+ {gcc_r11, dwarf_r11, LLDB_INVALID_REGNUM, gdb_arm_r11, gpr_r11},
+ NULL,
+ NULL},
+ {"r12",
+ NULL,
+ 4,
+ GPR_OFFSET(12),
+ eEncodingUint,
+ eFormatHex,
+ {gcc_r12, dwarf_r12, LLDB_INVALID_REGNUM, gdb_arm_r12, gpr_r12},
+ NULL,
+ NULL},
+ {"sp",
+ "r13",
+ 4,
+ GPR_OFFSET(13),
+ eEncodingUint,
+ eFormatHex,
+ {gcc_sp, dwarf_sp, LLDB_REGNUM_GENERIC_SP, gdb_arm_sp, gpr_sp},
+ NULL,
+ NULL},
+ {"lr",
+ "r14",
+ 4,
+ GPR_OFFSET(14),
+ eEncodingUint,
+ eFormatHex,
+ {gcc_lr, dwarf_lr, LLDB_REGNUM_GENERIC_RA, gdb_arm_lr, gpr_lr},
+ NULL,
+ NULL},
+ {"pc",
+ "r15",
+ 4,
+ GPR_OFFSET(15),
+ eEncodingUint,
+ eFormatHex,
+ {gcc_pc, dwarf_pc, LLDB_REGNUM_GENERIC_PC, gdb_arm_pc, gpr_pc},
+ NULL,
+ NULL},
+ {"cpsr",
+ "psr",
+ 4,
+ GPR_OFFSET(16),
+ eEncodingUint,
+ eFormatHex,
+ {gcc_cpsr, dwarf_cpsr, LLDB_REGNUM_GENERIC_FLAGS, gdb_arm_cpsr, gpr_cpsr},
+ NULL,
+ NULL},
+};
+
+const RegisterInfo *
+RegisterContextFreeBSD_arm::GetRegisterInfo() const
+{
+ switch (m_target_arch.GetMachine())
+ {
+ case llvm::Triple::arm:
+ return g_register_infos_arm;
+ default:
+ assert(false && "Unhandled target architecture.");
+ return NULL;
+ }
+}
+
+uint32_t
+RegisterContextFreeBSD_arm::GetRegisterCount() const
+{
+ return static_cast<uint32_t>(sizeof(g_register_infos_arm) / sizeof(g_register_infos_arm[0]));
+}
diff --git a/source/Plugins/Process/Utility/RegisterContextFreeBSD_arm.h b/source/Plugins/Process/Utility/RegisterContextFreeBSD_arm.h
new file mode 100644
index 0000000..f1f742a
--- /dev/null
+++ b/source/Plugins/Process/Utility/RegisterContextFreeBSD_arm.h
@@ -0,0 +1,27 @@
+//===-- RegisterContextFreeBSD_arm.h ---------------------------*- C++ -*-===//
+//
+// The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef liblldb_RegisterContextFreeBSD_arm_H_
+#define liblldb_RegisterContextFreeBSD_arm_H_
+
+#include "RegisterContextPOSIX.h"
+
+class RegisterContextFreeBSD_arm : public lldb_private::RegisterInfoInterface
+{
+ public:
+ RegisterContextFreeBSD_arm(const lldb_private::ArchSpec &target_arch);
+
+ size_t GetGPRSize() const override;
+
+ const lldb_private::RegisterInfo *GetRegisterInfo() const override;
+
+ uint32_t GetRegisterCount() const override;
+};
+
+#endif
diff --git a/source/Plugins/Process/Utility/RegisterContextPOSIX_arm.cpp b/source/Plugins/Process/Utility/RegisterContextPOSIX_arm.cpp
index b79cc76..d306f86 100644
--- a/source/Plugins/Process/Utility/RegisterContextPOSIX_arm.cpp
+++ b/source/Plugins/Process/Utility/RegisterContextPOSIX_arm.cpp
@@ -229,7 +229,7 @@ RegisterContextPOSIX_arm::GetRegisterSet(size_t set)
{
switch (m_register_info_ap->m_target_arch.GetMachine())
{
- case llvm::Triple::aarch64:
+ case llvm::Triple::arm:
return &g_reg_sets_arm[set];
default:
assert(false && "Unhandled target architecture.");
--
2.3.3
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