Author: tstellar Date: Fri Apr 11 16:04:44 2014 New Revision: 206071 URL: http://llvm.org/viewvc/llvm-project?rev=206071&view=rev Log: Merging r203581:
------------------------------------------------------------------------ r203581 | hans | 2014-03-11 11:49:24 -0400 (Tue, 11 Mar 2014) | 7 lines X86: Don't generate 64-bit movd after cmpneqsd in 32-bit mode (PR19059) This fixes the bug where we would bitcast the 64-bit floating point result of cmpneqsd to a 64-bit integer even on 32-bit targets. Differential Revision: http://llvm-reviews.chandlerc.com/D3009 ------------------------------------------------------------------------ Modified: llvm/branches/release_34/lib/Target/X86/X86ISelLowering.cpp llvm/branches/release_34/test/CodeGen/X86/isint.ll Modified: llvm/branches/release_34/lib/Target/X86/X86ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_34/lib/Target/X86/X86ISelLowering.cpp?rev=206071&r1=206070&r2=206071&view=diff ============================================================================== --- llvm/branches/release_34/lib/Target/X86/X86ISelLowering.cpp (original) +++ llvm/branches/release_34/lib/Target/X86/X86ISelLowering.cpp Fri Apr 11 16:04:44 2014 @@ -17583,12 +17583,30 @@ static SDValue CMPEQCombine(SDNode *N, S // FIXME: need symbolic constants for these magic numbers. // See X86ATTInstPrinter.cpp:printSSECC(). unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4; - SDValue OnesOrZeroesF = DAG.getNode(NTOperator, DL, MVT::f32, CMP00, CMP01, + SDValue OnesOrZeroesF = DAG.getNode(NTOperator, DL, CMP00.getValueType(), + CMP00, CMP01, DAG.getConstant(x86cc, MVT::i8)); - SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, MVT::i32, - OnesOrZeroesF); - SDValue ANDed = DAG.getNode(ISD::AND, DL, MVT::i32, OnesOrZeroesI, - DAG.getConstant(1, MVT::i32)); + + MVT IntVT = is64BitFP ? MVT::i64 : MVT::i32; + + if (is64BitFP && !Subtarget->is64Bit()) { + // On a 32-bit target, we cannot bitcast the 64-bit float to a + // 64-bit integer, since that's not a legal type. Since + // OnesOrZeroesF is all ones of all zeroes, we don't need all the + // bits, but can do this little dance to extract the lowest 32 bits + // and work with those going forward. + SDValue Vector64 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64, + OnesOrZeroesF); + SDValue Vector32 = DAG.getNode(ISD::BITCAST, DL, MVT::v4f32, + Vector64); + OnesOrZeroesF = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, + Vector32, DAG.getIntPtrConstant(0)); + IntVT = MVT::i32; + } + + SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, IntVT, OnesOrZeroesF); + SDValue ANDed = DAG.getNode(ISD::AND, DL, IntVT, OnesOrZeroesI, + DAG.getConstant(1, IntVT)); SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8, ANDed); return OneBitOfTruth; } Modified: llvm/branches/release_34/test/CodeGen/X86/isint.ll URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_34/test/CodeGen/X86/isint.ll?rev=206071&r1=206070&r2=206071&view=diff ============================================================================== --- llvm/branches/release_34/test/CodeGen/X86/isint.ll (original) +++ llvm/branches/release_34/test/CodeGen/X86/isint.ll Fri Apr 11 16:04:44 2014 @@ -1,6 +1,11 @@ -; RUN: llc < %s -march=x86 -mattr=+sse2 | FileCheck %s +; RUN: llc < %s -mtriple=x86_64-pc-unknown -mattr=+sse2 -mcpu=penryn | FileCheck %s +; RUN: llc < %s -mtriple=i686-pc-unknown -mattr=+sse2 -mcpu=penryn | FileCheck %s + +; PR19059 +; RUN: llc < %s -mtriple=i686-pc-unknown -mattr=+sse2 -mcpu=penryn | FileCheck -check-prefix=CHECK32 %s define i32 @isint_return(double %d) nounwind { +; CHECK-LABEL: isint_return: ; CHECK-NOT: xor ; CHECK: cvt %i = fptosi double %d to i32 @@ -8,6 +13,24 @@ define i32 @isint_return(double %d) noun %e = sitofp i32 %i to double ; CHECK: cmpeqsd %c = fcmp oeq double %d, %e +; CHECK32-NOT: movd {{.*}}, %r{{.*}} +; CHECK32-NOT: andq +; CHECK-NEXT: movd +; CHECK-NEXT: andl + %z = zext i1 %c to i32 + ret i32 %z +} + +define i32 @isint_float_return(float %f) nounwind { +; CHECK-LABEL: isint_float_return: +; CHECK-NOT: xor +; CHECK: cvt + %i = fptosi float %f to i32 +; CHECK-NEXT: cvt + %g = sitofp i32 %i to float +; CHECK: cmpeqss + %c = fcmp oeq float %f, %g +; CHECK-NOT: movd {{.*}}, %r{{.*}} ; CHECK-NEXT: movd ; CHECK-NEXT: andl %z = zext i1 %c to i32 @@ -17,6 +40,7 @@ define i32 @isint_return(double %d) noun declare void @foo() define void @isint_branch(double %d) nounwind { +; CHECK-LABEL: isint_branch: ; CHECK: cvt %i = fptosi double %d to i32 ; CHECK-NEXT: cvt _______________________________________________ llvm-branch-commits mailing list [email protected] http://lists.cs.uiuc.edu/mailman/listinfo/llvm-branch-commits
