Author: dsanders
Date: Mon Nov 24 15:42:40 2014
New Revision: 222693
URL: http://llvm.org/viewvc/llvm-project?rev=222693&view=rev
Log:
Merging r221453:
------------------------------------------------------------------------
r221453 | tomatabacu | 2014-11-06 14:25:42 +0000 (Thu, 06 Nov 2014) | 17 lines
[mips] Tolerate the use of the %z inline asm operand modifier with
non-immediates.
Summary:
Currently, we give an error if %z is used with non-immediates, instead of
continuing as if the %z isn't there.
For example, you use the %z operand modifier along with the "Jr" constraints
("r" makes the operand a register, and "J" makes it an immediate, but only if
its value is 0).
In this case, you want the compiler to print "$0" if the inline asm input
operand turns out to be an immediate zero and you want it to print the register
containing the operand, if it's not.
We give an error in the latter case, and we shouldn't (GCC also doesn't).
Reviewers: dsanders
Reviewed By: dsanders
Subscribers: llvm-commits
Differential Revision: http://reviews.llvm.org/D6023
------------------------------------------------------------------------
Modified:
llvm/branches/release_35/ (props changed)
llvm/branches/release_35/lib/Target/Mips/MipsAsmPrinter.cpp
llvm/branches/release_35/test/CodeGen/Mips/inlineasm-operand-code.ll
Propchange: llvm/branches/release_35/
------------------------------------------------------------------------------
--- svn:mergeinfo (original)
+++ svn:mergeinfo Mon Nov 24 15:42:40 2014
@@ -1,3 +1,3 @@
/llvm/branches/Apple/Pertwee:110850,110961
/llvm/branches/type-system-rewrite:133420-134817
-/llvm/trunk:155241,213653,213665,213726,213749,213773,213793,213798-213799,213815,213847,213880,213883-213884,213894-213896,213899,213915,213966,213999,214060,214129,214180,214287,214331,214423,214429,214519,214670,214674,214679,215685,215711,215806,216064,216531,216920,221408
+/llvm/trunk:155241,213653,213665,213726,213749,213773,213793,213798-213799,213815,213847,213880,213883-213884,213894-213896,213899,213915,213966,213999,214060,214129,214180,214287,214331,214423,214429,214519,214670,214674,214679,215685,215711,215806,216064,216531,216920,221408,221453
Modified: llvm/branches/release_35/lib/Target/Mips/MipsAsmPrinter.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/branches/release_35/lib/Target/Mips/MipsAsmPrinter.cpp?rev=222693&r1=222692&r2=222693&view=diff
==============================================================================
--- llvm/branches/release_35/lib/Target/Mips/MipsAsmPrinter.cpp (original)
+++ llvm/branches/release_35/lib/Target/Mips/MipsAsmPrinter.cpp Mon Nov 24
15:42:40 2014
@@ -471,14 +471,12 @@ bool MipsAsmPrinter::PrintAsmOperand(con
return false;
case 'z': {
// $0 if zero, regular printing otherwise
- if (MO.getType() != MachineOperand::MO_Immediate)
- return true;
- int64_t Val = MO.getImm();
- if (Val)
- O << Val;
- else
+ if (MO.getType() == MachineOperand::MO_Immediate && MO.getImm() == 0) {
O << "$0";
- return false;
+ return false;
+ }
+ // If not, call printOperand as normal.
+ break;
}
case 'D': // Second part of a double word register operand
case 'L': // Low order register of a double word register operand
Modified: llvm/branches/release_35/test/CodeGen/Mips/inlineasm-operand-code.ll
URL:
http://llvm.org/viewvc/llvm-project/llvm/branches/release_35/test/CodeGen/Mips/inlineasm-operand-code.ll?rev=222693&r1=222692&r2=222693&view=diff
==============================================================================
--- llvm/branches/release_35/test/CodeGen/Mips/inlineasm-operand-code.ll
(original)
+++ llvm/branches/release_35/test/CodeGen/Mips/inlineasm-operand-code.ll Mon
Nov 24 15:42:40 2014
@@ -65,6 +65,33 @@ entry:
;CHECK_LITTLE_32: addiu ${{[0-9]+}},${{[0-9]+}},$0
;CHECK_LITTLE_32: #NO_APP
tail call i32 asm sideeffect "addiu $0,$1,${2:z}", "=r,r,I"(i32 7, i32 0)
nounwind
+
+; z with non-zero and the "r"(register) and "J"(integer zero) constraints
+;CHECK_LITTLE_32: #APP
+;CHECK_LITTLE_32: mtc0 ${{[1-9][0-9]?}}, ${{[0-9]+}}
+;CHECK_LITTLE_32: #NO_APP
+ call void asm sideeffect "mtc0 ${0:z}, $$12", "Jr"(i32 7) nounwind
+
+; z with zero and the "r"(register) and "J"(integer zero) constraints
+;CHECK_LITTLE_32: #APP
+;CHECK_LITTLE_32: mtc0 $0, ${{[0-9]+}}
+;CHECK_LITTLE_32: #NO_APP
+ call void asm sideeffect "mtc0 ${0:z}, $$12", "Jr"(i32 0) nounwind
+
+; z with non-zero and just the "r"(register) constraint
+;CHECK_LITTLE_32: #APP
+;CHECK_LITTLE_32: mtc0 ${{[1-9][0-9]?}}, ${{[0-9]+}}
+;CHECK_LITTLE_32: #NO_APP
+ call void asm sideeffect "mtc0 ${0:z}, $$12", "r"(i32 7) nounwind
+
+; z with zero and just the "r"(register) constraint
+; FIXME: Check for $0, instead of other registers.
+; We should be using $0 directly in this case, not real registers.
+; When the materialization of 0 gets fixed, this test will fail.
+;CHECK_LITTLE_32: #APP
+;CHECK_LITTLE_32: mtc0 ${{[1-9][0-9]?}}, ${{[0-9]+}}
+;CHECK_LITTLE_32: #NO_APP
+ call void asm sideeffect "mtc0 ${0:z}, $$12", "r"(i32 0) nounwind
ret i32 0
}
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