Author: tstellar
Date: Thu Apr 23 14:14:38 2015
New Revision: 235621
URL: http://llvm.org/viewvc/llvm-project?rev=235621&view=rev
Log:
Merging r229223:
------------------------------------------------------------------------
r229223 | Matthew.Arsenault | 2015-02-13 21:51:44 -0500 (Fri, 13 Feb 2015) | 5
lines
R600/SI: Fix size of VReg_1
This is really a 32-bit register, if we try to check the size of it,
we want 32-bits.
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Modified:
llvm/branches/release_36/lib/Target/R600/SIRegisterInfo.td
Modified: llvm/branches/release_36/lib/Target/R600/SIRegisterInfo.td
URL:
http://llvm.org/viewvc/llvm-project/llvm/branches/release_36/lib/Target/R600/SIRegisterInfo.td?rev=235621&r1=235620&r2=235621&view=diff
==============================================================================
--- llvm/branches/release_36/lib/Target/R600/SIRegisterInfo.td (original)
+++ llvm/branches/release_36/lib/Target/R600/SIRegisterInfo.td Thu Apr 23
14:14:38 2015
@@ -209,7 +209,7 @@ def VReg_256 : RegisterClass<"AMDGPU", [
def VReg_512 : RegisterClass<"AMDGPU", [v16i32, v16f32], 512, (add VGPR_512)>;
-def VReg_1 : RegisterClass<"AMDGPU", [i1], 32, (add VGPR_32)>;
+def VReg_1 : RegisterClass<"AMDGPU", [i1, i32], 32, (add VGPR_32)>;
class RegImmOperand <RegisterClass rc> : RegisterOperand<rc> {
let OperandNamespace = "AMDGPU";
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