Author: tstellar Date: Tue May 30 15:36:49 2017 New Revision: 304242 URL: http://llvm.org/viewvc/llvm-project?rev=304242&view=rev Log: Merging r298179:
----------------------------------------------------------------------- r298179 | niravd | 2017-03-17 20:44:07 -0400 (Fri, 17 Mar 2017) | 7 lines Make library calls sensitive to regparm module flag (Fixes PR3997). Reviewers: mkuper, rnk Subscribers: mehdi_amini, jyknight, aemerson, llvm-commits, rengolin Differential Revision: https://reviews.llvm.org/D27050 ------------------------------------------------------------------------ Added: llvm/branches/release_40/test/CodeGen/X86/regparm.ll Modified: llvm/branches/release_40/include/llvm/CodeGen/FastISel.h llvm/branches/release_40/include/llvm/IR/Module.h llvm/branches/release_40/include/llvm/Target/TargetLowering.h llvm/branches/release_40/lib/CodeGen/SelectionDAG/FastISel.cpp llvm/branches/release_40/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp llvm/branches/release_40/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp llvm/branches/release_40/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp llvm/branches/release_40/lib/CodeGen/SelectionDAG/SelectionDAG.cpp llvm/branches/release_40/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp llvm/branches/release_40/lib/CodeGen/SelectionDAG/TargetLowering.cpp llvm/branches/release_40/lib/IR/Module.cpp llvm/branches/release_40/lib/Target/AArch64/AArch64ISelLowering.cpp llvm/branches/release_40/lib/Target/AArch64/AArch64SelectionDAGInfo.cpp llvm/branches/release_40/lib/Target/ARM/ARMISelLowering.cpp llvm/branches/release_40/lib/Target/ARM/ARMSelectionDAGInfo.cpp llvm/branches/release_40/lib/Target/AVR/AVRISelLowering.cpp llvm/branches/release_40/lib/Target/Hexagon/HexagonSelectionDAGInfo.cpp llvm/branches/release_40/lib/Target/Mips/MipsISelLowering.cpp llvm/branches/release_40/lib/Target/PowerPC/PPCISelLowering.cpp llvm/branches/release_40/lib/Target/X86/X86ISelLowering.cpp llvm/branches/release_40/lib/Target/X86/X86ISelLowering.h llvm/branches/release_40/lib/Target/X86/X86SelectionDAGInfo.cpp llvm/branches/release_40/lib/Target/XCore/XCoreISelLowering.cpp llvm/branches/release_40/lib/Target/XCore/XCoreSelectionDAGInfo.cpp Modified: llvm/branches/release_40/include/llvm/CodeGen/FastISel.h URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_40/include/llvm/CodeGen/FastISel.h?rev=304242&r1=304241&r2=304242&view=diff ============================================================================== --- llvm/branches/release_40/include/llvm/CodeGen/FastISel.h (original) +++ llvm/branches/release_40/include/llvm/CodeGen/FastISel.h Tue May 30 15:36:49 2017 @@ -57,6 +57,47 @@ public: }; typedef std::vector<ArgListEntry> ArgListTy; + // This is a workaround to not move around the ArgListEntryTypes. + void markFastLibCallAttributes(const TargetLowering &TL, MachineFunction *MF, + unsigned CC, ArgListTy &Args) const { + + TargetLowering::ArgListTy TLArgs; + // Convert to TargetLowering::ArgListTy + for (unsigned long i = 0; i < Args.size(); ++i) { + TargetLowering::ArgListEntry TArg; + TArg.Ty = Args[i].Ty; + TArg.isSExt = Args[i].IsSExt; + TArg.isZExt = Args[i].IsZExt; + TArg.isInReg = Args[i].IsInReg; + TArg.isSRet = Args[i].IsSRet; + TArg.isNest = Args[i].IsNest; + TArg.isByVal = Args[i].IsByVal; + TArg.isInAlloca = Args[i].IsInAlloca; + TArg.isReturned = Args[i].IsReturned; + TArg.isSwiftSelf = Args[i].IsSwiftSelf; + TArg.isSwiftError = Args[i].IsSwiftError; + TArg.Alignment = Args[i].Alignment; + TLArgs.push_back(TArg); + } + // Call convered + TL.markLibCallAttributes(MF, CC, TLArgs); + // Copy back. + for (unsigned long i = 0; i < Args.size(); ++i) { + Args[i].Ty = TLArgs[i].Ty; + Args[i].IsSExt = TLArgs[i].isSExt; + Args[i].IsZExt = TLArgs[i].isZExt; + Args[i].IsInReg = TLArgs[i].isInReg; + Args[i].IsSRet = TLArgs[i].isSRet; + Args[i].IsNest = TLArgs[i].isNest; + Args[i].IsByVal = TLArgs[i].isByVal; + Args[i].IsInAlloca = TLArgs[i].isInAlloca; + Args[i].IsReturned = TLArgs[i].isReturned; + Args[i].IsSwiftSelf = TLArgs[i].isSwiftSelf; + Args[i].IsSwiftError = TLArgs[i].isSwiftError; + Args[i].Alignment = TLArgs[i].Alignment; + } + } + struct CallLoweringInfo { Type *RetTy; bool RetSExt : 1; Modified: llvm/branches/release_40/include/llvm/IR/Module.h URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_40/include/llvm/IR/Module.h?rev=304242&r1=304241&r2=304242&view=diff ============================================================================== --- llvm/branches/release_40/include/llvm/IR/Module.h (original) +++ llvm/branches/release_40/include/llvm/IR/Module.h Tue May 30 15:36:49 2017 @@ -726,6 +726,10 @@ public: /// @name Utility functions for querying Debug information. /// @{ + /// \brief Returns the Number of Register ParametersDwarf Version by checking + /// module flags. + unsigned getNumberRegisterParameters() const; + /// \brief Returns the Dwarf Version by checking module flags. unsigned getDwarfVersion() const; Modified: llvm/branches/release_40/include/llvm/Target/TargetLowering.h URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_40/include/llvm/Target/TargetLowering.h?rev=304242&r1=304241&r2=304242&view=diff ============================================================================== --- llvm/branches/release_40/include/llvm/Target/TargetLowering.h (original) +++ llvm/branches/release_40/include/llvm/Target/TargetLowering.h Tue May 30 15:36:49 2017 @@ -25,13 +25,14 @@ #include "llvm/ADT/ArrayRef.h" #include "llvm/ADT/DenseMap.h" -#include "llvm/ADT/SmallVector.h" #include "llvm/ADT/STLExtras.h" +#include "llvm/ADT/SmallVector.h" #include "llvm/ADT/StringRef.h" #include "llvm/CodeGen/DAGCombine.h" #include "llvm/CodeGen/ISDOpcodes.h" #include "llvm/CodeGen/MachineValueType.h" #include "llvm/CodeGen/RuntimeLibcalls.h" +#include "llvm/CodeGen/SelectionDAG.h" #include "llvm/CodeGen/SelectionDAGNodes.h" #include "llvm/CodeGen/ValueTypes.h" #include "llvm/IR/Attributes.h" @@ -2560,6 +2561,9 @@ public: }; typedef std::vector<ArgListEntry> ArgListTy; + virtual void markLibCallAttributes(MachineFunction *MF, unsigned CC, + ArgListTy &Args) const {}; + /// This structure contains all information that is necessary for lowering /// calls. It is passed to TLI::LowerCallTo when the SelectionDAG builder /// needs to lower a call, and targets will see this struct in their LowerCall @@ -2609,6 +2613,20 @@ public: return *this; } + // setCallee with target/module-specific attributes + CallLoweringInfo &setLibCallee(CallingConv::ID CC, Type *ResultType, + SDValue Target, ArgListTy &&ArgsList) { + RetTy = ResultType; + Callee = Target; + CallConv = CC; + NumFixedArgs = Args.size(); + Args = std::move(ArgsList); + + DAG.getTargetLoweringInfo().markLibCallAttributes( + &(DAG.getMachineFunction()), CC, Args); + return *this; + } + CallLoweringInfo &setCallee(CallingConv::ID CC, Type *ResultType, SDValue Target, ArgListTy &&ArgsList) { RetTy = ResultType; Modified: llvm/branches/release_40/lib/CodeGen/SelectionDAG/FastISel.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_40/lib/CodeGen/SelectionDAG/FastISel.cpp?rev=304242&r1=304241&r2=304242&view=diff ============================================================================== --- llvm/branches/release_40/lib/CodeGen/SelectionDAG/FastISel.cpp (original) +++ llvm/branches/release_40/lib/CodeGen/SelectionDAG/FastISel.cpp Tue May 30 15:36:49 2017 @@ -888,6 +888,8 @@ bool FastISel::lowerCallTo(const CallIns Entry.setAttributes(&CS, ArgI + 1); Args.push_back(Entry); } + markFastLibCallAttributes(*MF->getSubtarget().getTargetLowering(), MF, + CS.getCallingConv(), Args); CallLoweringInfo CLI; CLI.setCallee(RetTy, FTy, Symbol, std::move(Args), CS, NumArgs); Modified: llvm/branches/release_40/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_40/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp?rev=304242&r1=304241&r2=304242&view=diff ============================================================================== --- llvm/branches/release_40/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (original) +++ llvm/branches/release_40/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Tue May 30 15:36:49 2017 @@ -1935,9 +1935,13 @@ SDValue SelectionDAGLegalize::ExpandLibC InChain = TCChain; TargetLowering::CallLoweringInfo CLI(DAG); - CLI.setDebugLoc(SDLoc(Node)).setChain(InChain) - .setCallee(TLI.getLibcallCallingConv(LC), RetTy, Callee, std::move(Args)) - .setTailCall(isTailCall).setSExtResult(isSigned).setZExtResult(!isSigned); + CLI.setDebugLoc(SDLoc(Node)) + .setChain(InChain) + .setLibCallee(TLI.getLibcallCallingConv(LC), RetTy, Callee, + std::move(Args)) + .setTailCall(isTailCall) + .setSExtResult(isSigned) + .setZExtResult(!isSigned); std::pair<SDValue, SDValue> CallInfo = TLI.LowerCallTo(CLI); @@ -1970,9 +1974,12 @@ SDValue SelectionDAGLegalize::ExpandLibC Type *RetTy = RetVT.getTypeForEVT(*DAG.getContext()); TargetLowering::CallLoweringInfo CLI(DAG); - CLI.setDebugLoc(dl).setChain(DAG.getEntryNode()) - .setCallee(TLI.getLibcallCallingConv(LC), RetTy, Callee, std::move(Args)) - .setSExtResult(isSigned).setZExtResult(!isSigned); + CLI.setDebugLoc(dl) + .setChain(DAG.getEntryNode()) + .setLibCallee(TLI.getLibcallCallingConv(LC), RetTy, Callee, + std::move(Args)) + .setSExtResult(isSigned) + .setZExtResult(!isSigned); std::pair<SDValue,SDValue> CallInfo = TLI.LowerCallTo(CLI); @@ -2004,9 +2011,12 @@ SelectionDAGLegalize::ExpandChainLibCall Type *RetTy = Node->getValueType(0).getTypeForEVT(*DAG.getContext()); TargetLowering::CallLoweringInfo CLI(DAG); - CLI.setDebugLoc(SDLoc(Node)).setChain(InChain) - .setCallee(TLI.getLibcallCallingConv(LC), RetTy, Callee, std::move(Args)) - .setSExtResult(isSigned).setZExtResult(!isSigned); + CLI.setDebugLoc(SDLoc(Node)) + .setChain(InChain) + .setLibCallee(TLI.getLibcallCallingConv(LC), RetTy, Callee, + std::move(Args)) + .setSExtResult(isSigned) + .setZExtResult(!isSigned); std::pair<SDValue, SDValue> CallInfo = TLI.LowerCallTo(CLI); @@ -2099,9 +2109,12 @@ SelectionDAGLegalize::ExpandDivRemLibCal SDLoc dl(Node); TargetLowering::CallLoweringInfo CLI(DAG); - CLI.setDebugLoc(dl).setChain(InChain) - .setCallee(TLI.getLibcallCallingConv(LC), RetTy, Callee, std::move(Args)) - .setSExtResult(isSigned).setZExtResult(!isSigned); + CLI.setDebugLoc(dl) + .setChain(InChain) + .setLibCallee(TLI.getLibcallCallingConv(LC), RetTy, Callee, + std::move(Args)) + .setSExtResult(isSigned) + .setZExtResult(!isSigned); std::pair<SDValue, SDValue> CallInfo = TLI.LowerCallTo(CLI); @@ -2210,9 +2223,9 @@ SelectionDAGLegalize::ExpandSinCosLibCal SDLoc dl(Node); TargetLowering::CallLoweringInfo CLI(DAG); - CLI.setDebugLoc(dl).setChain(InChain) - .setCallee(TLI.getLibcallCallingConv(LC), - Type::getVoidTy(*DAG.getContext()), Callee, std::move(Args)); + CLI.setDebugLoc(dl).setChain(InChain).setLibCallee( + TLI.getLibcallCallingConv(LC), Type::getVoidTy(*DAG.getContext()), Callee, + std::move(Args)); std::pair<SDValue, SDValue> CallInfo = TLI.LowerCallTo(CLI); @@ -3830,10 +3843,11 @@ void SelectionDAGLegalize::ConvertNodeTo TargetLowering::CallLoweringInfo CLI(DAG); CLI.setDebugLoc(dl) .setChain(Node->getOperand(0)) - .setCallee(CallingConv::C, Type::getVoidTy(*DAG.getContext()), - DAG.getExternalSymbol("__sync_synchronize", - TLI.getPointerTy(DAG.getDataLayout())), - std::move(Args)); + .setLibCallee( + CallingConv::C, Type::getVoidTy(*DAG.getContext()), + DAG.getExternalSymbol("__sync_synchronize", + TLI.getPointerTy(DAG.getDataLayout())), + std::move(Args)); std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI); @@ -3870,10 +3884,10 @@ void SelectionDAGLegalize::ConvertNodeTo TargetLowering::CallLoweringInfo CLI(DAG); CLI.setDebugLoc(dl) .setChain(Node->getOperand(0)) - .setCallee(CallingConv::C, Type::getVoidTy(*DAG.getContext()), - DAG.getExternalSymbol("abort", - TLI.getPointerTy(DAG.getDataLayout())), - std::move(Args)); + .setLibCallee(CallingConv::C, Type::getVoidTy(*DAG.getContext()), + DAG.getExternalSymbol( + "abort", TLI.getPointerTy(DAG.getDataLayout())), + std::move(Args)); std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI); Results.push_back(CallResult.second); Modified: llvm/branches/release_40/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_40/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp?rev=304242&r1=304241&r2=304242&view=diff ============================================================================== --- llvm/branches/release_40/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp (original) +++ llvm/branches/release_40/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp Tue May 30 15:36:49 2017 @@ -2601,9 +2601,10 @@ void DAGTypeLegalizer::ExpandIntRes_XMUL SDValue Func = DAG.getExternalSymbol(TLI.getLibcallName(LC), PtrVT); TargetLowering::CallLoweringInfo CLI(DAG); - CLI.setDebugLoc(dl).setChain(Chain) - .setCallee(TLI.getLibcallCallingConv(LC), RetTy, Func, std::move(Args)) - .setSExtResult(); + CLI.setDebugLoc(dl) + .setChain(Chain) + .setLibCallee(TLI.getLibcallCallingConv(LC), RetTy, Func, std::move(Args)) + .setSExtResult(); std::pair<SDValue, SDValue> CallInfo = TLI.LowerCallTo(CLI); Modified: llvm/branches/release_40/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_40/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp?rev=304242&r1=304241&r2=304242&view=diff ============================================================================== --- llvm/branches/release_40/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp (original) +++ llvm/branches/release_40/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp Tue May 30 15:36:49 2017 @@ -1087,9 +1087,12 @@ DAGTypeLegalizer::ExpandChainLibCall(RTL Type *RetTy = Node->getValueType(0).getTypeForEVT(*DAG.getContext()); TargetLowering::CallLoweringInfo CLI(DAG); - CLI.setDebugLoc(SDLoc(Node)).setChain(InChain) - .setCallee(TLI.getLibcallCallingConv(LC), RetTy, Callee, std::move(Args)) - .setSExtResult(isSigned).setZExtResult(!isSigned); + CLI.setDebugLoc(SDLoc(Node)) + .setChain(InChain) + .setLibCallee(TLI.getLibcallCallingConv(LC), RetTy, Callee, + std::move(Args)) + .setSExtResult(isSigned) + .setZExtResult(!isSigned); std::pair<SDValue, SDValue> CallInfo = TLI.LowerCallTo(CLI); Modified: llvm/branches/release_40/lib/CodeGen/SelectionDAG/SelectionDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_40/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=304242&r1=304241&r2=304242&view=diff ============================================================================== --- llvm/branches/release_40/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original) +++ llvm/branches/release_40/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Tue May 30 15:36:49 2017 @@ -4943,11 +4943,11 @@ SDValue SelectionDAG::getMemcpy(SDValue TargetLowering::CallLoweringInfo CLI(*this); CLI.setDebugLoc(dl) .setChain(Chain) - .setCallee(TLI->getLibcallCallingConv(RTLIB::MEMCPY), - Dst.getValueType().getTypeForEVT(*getContext()), - getExternalSymbol(TLI->getLibcallName(RTLIB::MEMCPY), - TLI->getPointerTy(getDataLayout())), - std::move(Args)) + .setLibCallee(TLI->getLibcallCallingConv(RTLIB::MEMCPY), + Dst.getValueType().getTypeForEVT(*getContext()), + getExternalSymbol(TLI->getLibcallName(RTLIB::MEMCPY), + TLI->getPointerTy(getDataLayout())), + std::move(Args)) .setDiscardResult() .setTailCall(isTailCall); @@ -5004,11 +5004,11 @@ SDValue SelectionDAG::getMemmove(SDValue TargetLowering::CallLoweringInfo CLI(*this); CLI.setDebugLoc(dl) .setChain(Chain) - .setCallee(TLI->getLibcallCallingConv(RTLIB::MEMMOVE), - Dst.getValueType().getTypeForEVT(*getContext()), - getExternalSymbol(TLI->getLibcallName(RTLIB::MEMMOVE), - TLI->getPointerTy(getDataLayout())), - std::move(Args)) + .setLibCallee(TLI->getLibcallCallingConv(RTLIB::MEMMOVE), + Dst.getValueType().getTypeForEVT(*getContext()), + getExternalSymbol(TLI->getLibcallName(RTLIB::MEMMOVE), + TLI->getPointerTy(getDataLayout())), + std::move(Args)) .setDiscardResult() .setTailCall(isTailCall); @@ -5066,11 +5066,11 @@ SDValue SelectionDAG::getMemset(SDValue TargetLowering::CallLoweringInfo CLI(*this); CLI.setDebugLoc(dl) .setChain(Chain) - .setCallee(TLI->getLibcallCallingConv(RTLIB::MEMSET), - Dst.getValueType().getTypeForEVT(*getContext()), - getExternalSymbol(TLI->getLibcallName(RTLIB::MEMSET), - TLI->getPointerTy(getDataLayout())), - std::move(Args)) + .setLibCallee(TLI->getLibcallCallingConv(RTLIB::MEMSET), + Dst.getValueType().getTypeForEVT(*getContext()), + getExternalSymbol(TLI->getLibcallName(RTLIB::MEMSET), + TLI->getPointerTy(getDataLayout())), + std::move(Args)) .setDiscardResult() .setTailCall(isTailCall); Modified: llvm/branches/release_40/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_40/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp?rev=304242&r1=304241&r2=304242&view=diff ============================================================================== --- llvm/branches/release_40/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp (original) +++ llvm/branches/release_40/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Tue May 30 15:36:49 2017 @@ -4929,14 +4929,12 @@ SelectionDAGBuilder::visitIntrinsicCall( report_fatal_error("Unsupported element size"); TargetLowering::CallLoweringInfo CLI(DAG); - CLI.setDebugLoc(sdl) - .setChain(getRoot()) - .setCallee(TLI.getLibcallCallingConv(LibraryCall), - Type::getVoidTy(*DAG.getContext()), - DAG.getExternalSymbol( - TLI.getLibcallName(LibraryCall), - TLI.getPointerTy(DAG.getDataLayout())), - std::move(Args)); + CLI.setDebugLoc(sdl).setChain(getRoot()).setLibCallee( + TLI.getLibcallCallingConv(LibraryCall), + Type::getVoidTy(*DAG.getContext()), + DAG.getExternalSymbol(TLI.getLibcallName(LibraryCall), + TLI.getPointerTy(DAG.getDataLayout())), + std::move(Args)); std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI); DAG.setRoot(CallResult.second); @@ -5548,7 +5546,7 @@ SelectionDAGBuilder::visitIntrinsicCall( TargetLowering::ArgListTy Args; TargetLowering::CallLoweringInfo CLI(DAG); - CLI.setDebugLoc(sdl).setChain(getRoot()).setCallee( + CLI.setDebugLoc(sdl).setChain(getRoot()).setLibCallee( CallingConv::C, I.getType(), DAG.getExternalSymbol(TrapFuncName.data(), TLI.getPointerTy(DAG.getDataLayout())), Modified: llvm/branches/release_40/lib/CodeGen/SelectionDAG/TargetLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_40/lib/CodeGen/SelectionDAG/TargetLowering.cpp?rev=304242&r1=304241&r2=304242&view=diff ============================================================================== --- llvm/branches/release_40/lib/CodeGen/SelectionDAG/TargetLowering.cpp (original) +++ llvm/branches/release_40/lib/CodeGen/SelectionDAG/TargetLowering.cpp Tue May 30 15:36:49 2017 @@ -138,10 +138,13 @@ TargetLowering::makeLibCall(SelectionDAG Type *RetTy = RetVT.getTypeForEVT(*DAG.getContext()); TargetLowering::CallLoweringInfo CLI(DAG); bool signExtend = shouldSignExtendTypeInLibCall(RetVT, isSigned); - CLI.setDebugLoc(dl).setChain(DAG.getEntryNode()) - .setCallee(getLibcallCallingConv(LC), RetTy, Callee, std::move(Args)) - .setNoReturn(doesNotReturn).setDiscardResult(!isReturnValueUsed) - .setSExtResult(signExtend).setZExtResult(!signExtend); + CLI.setDebugLoc(dl) + .setChain(DAG.getEntryNode()) + .setLibCallee(getLibcallCallingConv(LC), RetTy, Callee, std::move(Args)) + .setNoReturn(doesNotReturn) + .setDiscardResult(!isReturnValueUsed) + .setSExtResult(signExtend) + .setZExtResult(!signExtend); return LowerCallTo(CLI); } @@ -3808,7 +3811,7 @@ SDValue TargetLowering::LowerToTLSEmulat TargetLowering::CallLoweringInfo CLI(DAG); CLI.setDebugLoc(dl).setChain(DAG.getEntryNode()); - CLI.setCallee(CallingConv::C, VoidPtrType, EmuTlsGetAddr, std::move(Args)); + CLI.setLibCallee(CallingConv::C, VoidPtrType, EmuTlsGetAddr, std::move(Args)); std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI); // TLSADDR will be codegen'ed as call. Inform MFI that function has calls. Modified: llvm/branches/release_40/lib/IR/Module.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_40/lib/IR/Module.cpp?rev=304242&r1=304241&r2=304242&view=diff ============================================================================== --- llvm/branches/release_40/lib/IR/Module.cpp (original) +++ llvm/branches/release_40/lib/IR/Module.cpp Tue May 30 15:36:49 2017 @@ -465,6 +465,14 @@ void Module::dropAllReferences() { GIF.dropAllReferences(); } +unsigned Module::getNumberRegisterParameters() const { + auto *Val = + cast_or_null<ConstantAsMetadata>(getModuleFlag("NumRegisterParameters")); + if (!Val) + return 0; + return cast<ConstantInt>(Val->getValue())->getZExtValue(); +} + unsigned Module::getDwarfVersion() const { auto *Val = cast_or_null<ConstantAsMetadata>(getModuleFlag("Dwarf Version")); if (!Val) Modified: llvm/branches/release_40/lib/Target/AArch64/AArch64ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_40/lib/Target/AArch64/AArch64ISelLowering.cpp?rev=304242&r1=304241&r2=304242&view=diff ============================================================================== --- llvm/branches/release_40/lib/Target/AArch64/AArch64ISelLowering.cpp (original) +++ llvm/branches/release_40/lib/Target/AArch64/AArch64ISelLowering.cpp Tue May 30 15:36:49 2017 @@ -2124,8 +2124,9 @@ SDValue AArch64TargetLowering::LowerFSIN StructType *RetTy = StructType::get(ArgTy, ArgTy, nullptr); TargetLowering::CallLoweringInfo CLI(DAG); - CLI.setDebugLoc(dl).setChain(DAG.getEntryNode()) - .setCallee(CallingConv::Fast, RetTy, Callee, std::move(Args)); + CLI.setDebugLoc(dl) + .setChain(DAG.getEntryNode()) + .setLibCallee(CallingConv::Fast, RetTy, Callee, std::move(Args)); std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI); return CallResult.first; Modified: llvm/branches/release_40/lib/Target/AArch64/AArch64SelectionDAGInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_40/lib/Target/AArch64/AArch64SelectionDAGInfo.cpp?rev=304242&r1=304241&r2=304242&view=diff ============================================================================== --- llvm/branches/release_40/lib/Target/AArch64/AArch64SelectionDAGInfo.cpp (original) +++ llvm/branches/release_40/lib/Target/AArch64/AArch64SelectionDAGInfo.cpp Tue May 30 15:36:49 2017 @@ -42,10 +42,12 @@ SDValue AArch64SelectionDAGInfo::EmitTar Entry.Node = Size; Args.push_back(Entry); TargetLowering::CallLoweringInfo CLI(DAG); - CLI.setDebugLoc(dl).setChain(Chain) - .setCallee(CallingConv::C, Type::getVoidTy(*DAG.getContext()), - DAG.getExternalSymbol(bzeroEntry, IntPtr), std::move(Args)) - .setDiscardResult(); + CLI.setDebugLoc(dl) + .setChain(Chain) + .setLibCallee(CallingConv::C, Type::getVoidTy(*DAG.getContext()), + DAG.getExternalSymbol(bzeroEntry, IntPtr), + std::move(Args)) + .setDiscardResult(); std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI); return CallResult.second; } Modified: llvm/branches/release_40/lib/Target/ARM/ARMISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_40/lib/Target/ARM/ARMISelLowering.cpp?rev=304242&r1=304241&r2=304242&view=diff ============================================================================== --- llvm/branches/release_40/lib/Target/ARM/ARMISelLowering.cpp (original) +++ llvm/branches/release_40/lib/Target/ARM/ARMISelLowering.cpp Tue May 30 15:36:49 2017 @@ -2790,9 +2790,9 @@ ARMTargetLowering::LowerToTLSGeneralDyna // FIXME: is there useful debug info available here? TargetLowering::CallLoweringInfo CLI(DAG); - CLI.setDebugLoc(dl).setChain(Chain) - .setCallee(CallingConv::C, Type::getInt32Ty(*DAG.getContext()), - DAG.getExternalSymbol("__tls_get_addr", PtrVT), std::move(Args)); + CLI.setDebugLoc(dl).setChain(Chain).setLibCallee( + CallingConv::C, Type::getInt32Ty(*DAG.getContext()), + DAG.getExternalSymbol("__tls_get_addr", PtrVT), std::move(Args)); std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI); return CallResult.first; Modified: llvm/branches/release_40/lib/Target/ARM/ARMSelectionDAGInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_40/lib/Target/ARM/ARMSelectionDAGInfo.cpp?rev=304242&r1=304241&r2=304242&view=diff ============================================================================== --- llvm/branches/release_40/lib/Target/ARM/ARMSelectionDAGInfo.cpp (original) +++ llvm/branches/release_40/lib/Target/ARM/ARMSelectionDAGInfo.cpp Tue May 30 15:36:49 2017 @@ -114,11 +114,11 @@ SDValue ARMSelectionDAGInfo::EmitSpecial TargetLowering::CallLoweringInfo CLI(DAG); CLI.setDebugLoc(dl) .setChain(Chain) - .setCallee( - TLI->getLibcallCallingConv(LC), Type::getVoidTy(*DAG.getContext()), - DAG.getExternalSymbol(FunctionNames[AEABILibcall][AlignVariant], - TLI->getPointerTy(DAG.getDataLayout())), - std::move(Args)) + .setLibCallee( + TLI->getLibcallCallingConv(LC), Type::getVoidTy(*DAG.getContext()), + DAG.getExternalSymbol(FunctionNames[AEABILibcall][AlignVariant], + TLI->getPointerTy(DAG.getDataLayout())), + std::move(Args)) .setDiscardResult(); std::pair<SDValue,SDValue> CallResult = TLI->LowerCallTo(CLI); Modified: llvm/branches/release_40/lib/Target/AVR/AVRISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_40/lib/Target/AVR/AVRISelLowering.cpp?rev=304242&r1=304241&r2=304242&view=diff ============================================================================== --- llvm/branches/release_40/lib/Target/AVR/AVRISelLowering.cpp (original) +++ llvm/branches/release_40/lib/Target/AVR/AVRISelLowering.cpp Tue May 30 15:36:49 2017 @@ -354,7 +354,7 @@ SDValue AVRTargetLowering::LowerDivRem(S TargetLowering::CallLoweringInfo CLI(DAG); CLI.setDebugLoc(dl) .setChain(InChain) - .setCallee(getLibcallCallingConv(LC), RetTy, Callee, std::move(Args)) + .setLibCallee(getLibcallCallingConv(LC), RetTy, Callee, std::move(Args)) .setInRegister() .setSExtResult(isSigned) .setZExtResult(!isSigned); Modified: llvm/branches/release_40/lib/Target/Hexagon/HexagonSelectionDAGInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_40/lib/Target/Hexagon/HexagonSelectionDAGInfo.cpp?rev=304242&r1=304241&r2=304242&view=diff ============================================================================== --- llvm/branches/release_40/lib/Target/Hexagon/HexagonSelectionDAGInfo.cpp (original) +++ llvm/branches/release_40/lib/Target/Hexagon/HexagonSelectionDAGInfo.cpp Tue May 30 15:36:49 2017 @@ -51,11 +51,12 @@ SDValue HexagonSelectionDAGInfo::EmitTar TargetLowering::CallLoweringInfo CLI(DAG); CLI.setDebugLoc(dl) .setChain(Chain) - .setCallee(TLI.getLibcallCallingConv(RTLIB::MEMCPY), - Type::getVoidTy(*DAG.getContext()), - DAG.getTargetExternalSymbol(SpecialMemcpyName, - TLI.getPointerTy(DAG.getDataLayout()), Flags), - std::move(Args)) + .setLibCallee( + TLI.getLibcallCallingConv(RTLIB::MEMCPY), + Type::getVoidTy(*DAG.getContext()), + DAG.getTargetExternalSymbol( + SpecialMemcpyName, TLI.getPointerTy(DAG.getDataLayout()), Flags), + std::move(Args)) .setDiscardResult(); std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI); Modified: llvm/branches/release_40/lib/Target/Mips/MipsISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_40/lib/Target/Mips/MipsISelLowering.cpp?rev=304242&r1=304241&r2=304242&view=diff ============================================================================== --- llvm/branches/release_40/lib/Target/Mips/MipsISelLowering.cpp (original) +++ llvm/branches/release_40/lib/Target/Mips/MipsISelLowering.cpp Tue May 30 15:36:49 2017 @@ -1820,8 +1820,9 @@ lowerGlobalTLSAddress(SDValue Op, Select Args.push_back(Entry); TargetLowering::CallLoweringInfo CLI(DAG); - CLI.setDebugLoc(DL).setChain(DAG.getEntryNode()) - .setCallee(CallingConv::C, PtrTy, TlsGetAddr, std::move(Args)); + CLI.setDebugLoc(DL) + .setChain(DAG.getEntryNode()) + .setLibCallee(CallingConv::C, PtrTy, TlsGetAddr, std::move(Args)); std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI); SDValue Ret = CallResult.first; Modified: llvm/branches/release_40/lib/Target/PowerPC/PPCISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_40/lib/Target/PowerPC/PPCISelLowering.cpp?rev=304242&r1=304241&r2=304242&view=diff ============================================================================== --- llvm/branches/release_40/lib/Target/PowerPC/PPCISelLowering.cpp (original) +++ llvm/branches/release_40/lib/Target/PowerPC/PPCISelLowering.cpp Tue May 30 15:36:49 2017 @@ -2602,10 +2602,9 @@ SDValue PPCTargetLowering::LowerINIT_TRA // Lower to a call to __trampoline_setup(Trmp, TrampSize, FPtr, ctx_reg) TargetLowering::CallLoweringInfo CLI(DAG); - CLI.setDebugLoc(dl).setChain(Chain) - .setCallee(CallingConv::C, Type::getVoidTy(*DAG.getContext()), - DAG.getExternalSymbol("__trampoline_setup", PtrVT), - std::move(Args)); + CLI.setDebugLoc(dl).setChain(Chain).setLibCallee( + CallingConv::C, Type::getVoidTy(*DAG.getContext()), + DAG.getExternalSymbol("__trampoline_setup", PtrVT), std::move(Args)); std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI); return CallResult.second; Modified: llvm/branches/release_40/lib/Target/X86/X86ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_40/lib/Target/X86/X86ISelLowering.cpp?rev=304242&r1=304241&r2=304242&view=diff ============================================================================== --- llvm/branches/release_40/lib/Target/X86/X86ISelLowering.cpp (original) +++ llvm/branches/release_40/lib/Target/X86/X86ISelLowering.cpp Tue May 30 15:36:49 2017 @@ -53,6 +53,7 @@ #include "llvm/Support/Debug.h" #include "llvm/Support/ErrorHandling.h" #include "llvm/Support/MathExtras.h" +#include "llvm/Target/TargetLowering.h" #include "llvm/Target/TargetOptions.h" #include <algorithm> #include <bitset> @@ -1933,6 +1934,34 @@ bool X86TargetLowering::useSoftFloat() c return Subtarget.useSoftFloat(); } +void X86TargetLowering::markLibCallAttributes(MachineFunction *MF, unsigned CC, + ArgListTy &Args) const { + + // Only relabel X86-32 for C / Stdcall CCs. + if (static_cast<const X86Subtarget &>(MF->getSubtarget()).is64Bit()) + return; + if (CC != CallingConv::C && CC != CallingConv::X86_StdCall) + return; + unsigned ParamRegs = 0; + if (auto *M = MF->getFunction()->getParent()) + ParamRegs = M->getNumberRegisterParameters(); + + // Mark the first N int arguments as having reg + for (unsigned Idx = 0; Idx < Args.size(); Idx++) { + Type *T = Args[Idx].Ty; + if (T->isPointerTy() || T->isIntegerTy()) + if (MF->getDataLayout().getTypeAllocSize(T) <= 8) { + unsigned numRegs = 1; + if (MF->getDataLayout().getTypeAllocSize(T) > 4) + numRegs = 2; + if (ParamRegs < numRegs) + return; + ParamRegs -= numRegs; + Args[Idx].isInReg = true; + } + } +} + const MCExpr * X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI, const MachineBasicBlock *MBB, @@ -21157,11 +21186,15 @@ SDValue X86TargetLowering::LowerWin64_i1 getPointerTy(DAG.getDataLayout())); TargetLowering::CallLoweringInfo CLI(DAG); - CLI.setDebugLoc(dl).setChain(InChain) - .setCallee(getLibcallCallingConv(LC), - static_cast<EVT>(MVT::v2i64).getTypeForEVT(*DAG.getContext()), - Callee, std::move(Args)) - .setInRegister().setSExtResult(isSigned).setZExtResult(!isSigned); + CLI.setDebugLoc(dl) + .setChain(InChain) + .setLibCallee( + getLibcallCallingConv(LC), + static_cast<EVT>(MVT::v2i64).getTypeForEVT(*DAG.getContext()), Callee, + std::move(Args)) + .setInRegister() + .setSExtResult(isSigned) + .setZExtResult(!isSigned); std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI); return DAG.getBitcast(VT, CallInfo.first); @@ -22885,8 +22918,9 @@ static SDValue LowerFSINCOS(SDValue Op, : (Type*)VectorType::get(ArgTy, 4); TargetLowering::CallLoweringInfo CLI(DAG); - CLI.setDebugLoc(dl).setChain(DAG.getEntryNode()) - .setCallee(CallingConv::C, RetTy, Callee, std::move(Args)); + CLI.setDebugLoc(dl) + .setChain(DAG.getEntryNode()) + .setLibCallee(CallingConv::C, RetTy, Callee, std::move(Args)); std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI); Modified: llvm/branches/release_40/lib/Target/X86/X86ISelLowering.h URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_40/lib/Target/X86/X86ISelLowering.h?rev=304242&r1=304241&r2=304242&view=diff ============================================================================== --- llvm/branches/release_40/lib/Target/X86/X86ISelLowering.h (original) +++ llvm/branches/release_40/lib/Target/X86/X86ISelLowering.h Tue May 30 15:36:49 2017 @@ -686,6 +686,9 @@ namespace llvm { unsigned getJumpTableEncoding() const override; bool useSoftFloat() const override; + void markLibCallAttributes(MachineFunction *MF, unsigned CC, + ArgListTy &Args) const override; + MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override { return MVT::i8; } Modified: llvm/branches/release_40/lib/Target/X86/X86SelectionDAGInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_40/lib/Target/X86/X86SelectionDAGInfo.cpp?rev=304242&r1=304241&r2=304242&view=diff ============================================================================== --- llvm/branches/release_40/lib/Target/X86/X86SelectionDAGInfo.cpp (original) +++ llvm/branches/release_40/lib/Target/X86/X86SelectionDAGInfo.cpp Tue May 30 15:36:49 2017 @@ -85,10 +85,12 @@ SDValue X86SelectionDAGInfo::EmitTargetC Args.push_back(Entry); TargetLowering::CallLoweringInfo CLI(DAG); - CLI.setDebugLoc(dl).setChain(Chain) - .setCallee(CallingConv::C, Type::getVoidTy(*DAG.getContext()), - DAG.getExternalSymbol(bzeroEntry, IntPtr), std::move(Args)) - .setDiscardResult(); + CLI.setDebugLoc(dl) + .setChain(Chain) + .setLibCallee(CallingConv::C, Type::getVoidTy(*DAG.getContext()), + DAG.getExternalSymbol(bzeroEntry, IntPtr), + std::move(Args)) + .setDiscardResult(); std::pair<SDValue,SDValue> CallResult = TLI.LowerCallTo(CLI); return CallResult.second; Modified: llvm/branches/release_40/lib/Target/XCore/XCoreISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_40/lib/Target/XCore/XCoreISelLowering.cpp?rev=304242&r1=304241&r2=304242&view=diff ============================================================================== --- llvm/branches/release_40/lib/Target/XCore/XCoreISelLowering.cpp (original) +++ llvm/branches/release_40/lib/Target/XCore/XCoreISelLowering.cpp Tue May 30 15:36:49 2017 @@ -483,7 +483,7 @@ LowerLOAD(SDValue Op, SelectionDAG &DAG) Args.push_back(Entry); TargetLowering::CallLoweringInfo CLI(DAG); - CLI.setDebugLoc(DL).setChain(Chain).setCallee( + CLI.setDebugLoc(DL).setChain(Chain).setLibCallee( CallingConv::C, IntPtrTy, DAG.getExternalSymbol("__misaligned_load", getPointerTy(DAG.getDataLayout())), Modified: llvm/branches/release_40/lib/Target/XCore/XCoreSelectionDAGInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_40/lib/Target/XCore/XCoreSelectionDAGInfo.cpp?rev=304242&r1=304241&r2=304242&view=diff ============================================================================== --- llvm/branches/release_40/lib/Target/XCore/XCoreSelectionDAGInfo.cpp (original) +++ llvm/branches/release_40/lib/Target/XCore/XCoreSelectionDAGInfo.cpp Tue May 30 15:36:49 2017 @@ -35,11 +35,11 @@ SDValue XCoreSelectionDAGInfo::EmitTarge TargetLowering::CallLoweringInfo CLI(DAG); CLI.setDebugLoc(dl) .setChain(Chain) - .setCallee(TLI.getLibcallCallingConv(RTLIB::MEMCPY), - Type::getVoidTy(*DAG.getContext()), - DAG.getExternalSymbol("__memcpy_4", - TLI.getPointerTy(DAG.getDataLayout())), - std::move(Args)) + .setLibCallee(TLI.getLibcallCallingConv(RTLIB::MEMCPY), + Type::getVoidTy(*DAG.getContext()), + DAG.getExternalSymbol( + "__memcpy_4", TLI.getPointerTy(DAG.getDataLayout())), + std::move(Args)) .setDiscardResult(); std::pair<SDValue,SDValue> CallResult = TLI.LowerCallTo(CLI); Added: llvm/branches/release_40/test/CodeGen/X86/regparm.ll URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_40/test/CodeGen/X86/regparm.ll?rev=304242&view=auto ============================================================================== --- llvm/branches/release_40/test/CodeGen/X86/regparm.ll (added) +++ llvm/branches/release_40/test/CodeGen/X86/regparm.ll Tue May 30 15:36:49 2017 @@ -0,0 +1,48 @@ +; RUN: llc %s -mtriple=i386-pc-linux -o - | FileCheck -check-prefix=CHECK %s +; RUN: llc %s -mtriple=i386-pc-win32 -o - | FileCheck -check-prefix=WIN %s +; RUN: llc %s -mtriple=i386-pc-linux -fast-isel -o - | FileCheck -check-prefix=FAST %s +; RUN: llc %s -mtriple=i386-pc-win32 -fast-isel -o - | FileCheck -check-prefix=FASTWIN %s + + + +target datalayout = "e-m:e-p:32:32-f64:32:64-f80:32-n8:16:32-S128" +target triple = "i386-unknown-linux-gnu" + +; Function Attrs: argmemonly nounwind +declare void @llvm.memcpy.p0i8.p0i8.i32(i8* nocapture writeonly, i8* nocapture readonly, i32, i32, i1) #1 + +define void @use_memset(i8* inreg nocapture %dest, i8 inreg %c, i32 inreg %n) local_unnamed_addr #0 { +entry: +;CHECK-LABEL: @use_memset +;CHECK-NOT: push +;CHECK: jmp memset +;CHECK-NOT: retl +;WIN-LABEL: @use_memset +;WIN-NOT: push +;WIN: jmp _memset +;WIN-NOT: retl +;FAST-LABEL: @use_memset +;FAST: subl $12, %esp +;FAST-NEXT: movzbl %dl, %edx +;FAST-NEXT: calll memset +;FAST-NEXT: addl $12, %esp +;FASTWIN-LABEL: @use_memset +;FASTWIN: movzbl %dl, %edx +;FASTWIN-NEXT: calll _memset +;FASTWIN-NEXT: retl + tail call void @llvm.memset.p0i8.i32(i8* %dest, i8 %c, i32 %n, i32 1, i1 false) + ret void +} + +; Function Attrs: argmemonly nounwind +declare void @llvm.memset.p0i8.i32(i8* nocapture writeonly, i8, i32, i32, i1) #1 + + +attributes #0 = { nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="pentium4" "target-features"="+fxsr,+mmx,+sse,+sse2,+x87" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #1 = { argmemonly nounwind } + +!llvm.module.flags = !{!0} +!llvm.ident = !{!1} + +!0 = !{i32 1, !"NumRegisterParameters", i32 3} +!1 = !{!"clang version 4.0.0 (trunk 288025) (llvm/trunk 288033)"} _______________________________________________ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
